Texas Instruments DAC3484, DAC3482 installation instructions Digital Block Options

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Software Control

2.2.2Digital Block Options

Figure 4. Digital Block Options

Interpolation: allows control of the data rate versus DAC sampling rate ratio (i.e. data rate × interpolation = DAC sampling rate).

Digital Mixer: allows control of the coarse mixer function.

Note: If fine mixer (NCO) is used, the “Enable Mixer” button must be checked, and the coarse mixer must be bypassed. See NCO section for detail.

Inverse sinx/x filter: allows compensation of the sinx/x attenuation of the DAC output.

Note: If inverse sinx/x filter is used, the input data digital full-scale must be backed off accordingly to avoid digital saturation.

Clock Receiver Sleep: allows the DAC clock receiver to be in sleep mode. The DAC has minimum power consumption in this mode.

Clock Divider Sync: allows the syncing of the internal divided-down clocks using either Frame, Sync, or OSTR signal. Enable the divider sync as part of the initialization procedure or resynchronization procedure.

Group Delay: allows adjustment of group delay for each I/Q channel. This is useful for wideband sideband suppression.

Offset Adjustment: allows adjustment of DC offset to minimize the LO feed-through of the modulator output. This section requires sync for proper operation. The sync options are listed below:

O REGWR: auto-sync from SIF register write.

OOSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with OSTR set as sync source

O SYNC: sync from the external LVDS SYNC signal.

OSIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.

QMC Adjustment: allows adjustment of the gain and phase of the I/Q channel to minimize sideband power of the modulator output.

OREGWR: auto-sync from SIF register write.

OOSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with OSTR set as sync source

O SYNC: sync from the external LVDS SYNC signal.

OSIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.

SLAU336 –March 2011

DAC3484/DAC3482 EVM

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Contents DAC3484/DAC3482 EVM Overview EVM Block DiagramInput Control Options Installation InstructionsSoftware Operation Lvds Delay Settings Digital Block Options Output Control Options CDCE62005 CDCE62005 Tab Configured for 4x InterpolationRegister Control Test Block DiagramMiscellaneous Settings TSW3100 Quick Start Operation Test Set-Up ConnectionDAC348x Software Quick Start Guide TSW3100 CommsSignalPattern Wcdma Programming GUIDAC3484 + TRF3703-15 Wcdma Output Optional Configuration Locations of DAC348x to Transformer Output Jumper Locations DAC3484 Transformer Coupled Output at 60MHz if DAC3484 Transformer Coupled Output at 30MHz if Using the DAC3482 or Configuring DAC3484 in DAC3482 modeLocations of the DAC3482 to TRF3703-15 Interface Jumpers Submit Documentation Feedback EVM Warnings and Restrictions Evaluation Board/Kit Important NoticeFCC Warning Important Notice