Overview, EVM Block Diagram | Texas Instruments DAC3482, DAC3484

Introduction

www.ti.com

1 Introduction

1.1Overview

This document is intended to serve as a basic user’s guide for the DAC3484/2 EVM Revision D. The EVM provides a basic platform to evaluate the DAC3484 and DAC3482, which are a family of 1.25GSPS, up to 16x interpolation, 16-bit high speed digital-to-analog converters. The DAC3484 is a quad-channel DAC, and the DAC3482 is a dual-channel DAC.

The EVM includes the CDCE62005 clocking source which provides the clocks required for the DAC and the pattern generator. The on-board TRF3703-15 modulators provide on-board IF-to-RF upconversion for basic transmitter evaluation. This EVM is ideally suited for mating with the TSW3100 pattern generation card for evaluating WCDMA, LTE, or other high performance modulation schemes.

1.2EVM Block Diagram

Figure 1 shows the configuration of the EVM with the TSW3100 used for pattern generation.

19.2 MHz Reference

LVCMOS Level Secondary Reference for CDCE62005 PLL Mode

J9	Ext. CLK Input
J9	1.5 Vrms Single Ended
	1.25GHz Max
	Primary Reference
	(LVPECL AC coupled )

19.2MHz	SEC	PRI
TCXO
		Y4

	CDCE62005
FPGA CLK	Y3

TSW3100	Y1	Y2
LVPECL DC coupled
OSTR_CLK		DAC_CLK
(LVPECL AC		(LVPECL AC
Coupled)		Coupled)

Ext. CLK Output

J10 J11

+	J7
_

Default TRF3703-15

Output

DATA

DATA _CLK

FRAME

SYNC

PARITY

(LVDS DC Coupled)

Power

Supply

Circuits

DAC348X

+	J6
_
+	J3
_
+	J2

J20 RF

TRF3703-15

J19 LO

J23 RF

TRF3703-15

J24 LO

Default TRF3703-15

Output

J21 RF

TRF3703-15

J22 LO

6 V Only

Optional DAC Output

Optional TRF3703-15 Output for DAC3482 Dual DAC Mode

Figure 1. DAC3484/DAC3482 EVM Block Diagram

2	DAC3484/DAC3482 EVM	SLAU336 –March 2011
		Submit Documentation Feedback