JAI CV-A1-20 Input and Output Circuits, Video output, Trigger input, HD and VD input

CV-A1-20

5.3. Input and Output Circuits

In the following schematic diagrams the input and output circuits for video and timing signals are shown. For alternative connections refer to “7.4. Internal Switch and Jumper Settings.” Jumper settings are shown as for factory default.

5.3.1. Video output

The video output is a 75 Ω DC coupled circuit. The BNC connector and pin #4 on the 12-pin connector is in parallel. Avoid double termination. The video DC level is shown with 75 Ω termination.

In the composite signal, there are no equalize and serration pulses in the vertical sync.

CXA1310

75

32

NC

#4/12

Video	300 mV
Output
BNC	500 mV
GND

Fig. 4. Video output.

5.3.2. Trigger input	+12v	JP1
The trigger input is AC coupled. To allow a
	Trigger #11/12	JP4	100		+5V
long pulse width, the input circuit is a flip				33k
flop, which is toggled by the negative or	input
positive differentiated spikes caused by the	#5/6		100n	1k	TTL
falling or rising trigger edges.				33k
					100k
The trigger polarity can be changed.
Trigger input level 4 V ±2 V.	GND	1k	NC	1n	1k
The trigger-input impedance is 1 kΩ.
					GND

JP1 and JP4 are for alternative configuration for pin #10.

Fig. 5. Trigger input.

5.3.3. HD and VD input

The input circuit for external HD and VD signals are shown. It can be 75 Ω terminated by closing SW2. SW1 will switch to output the internal HD and VD signal. HD and VD input level is 4 V ±2 V.

VD HD

Input/output

1n

GND

From VD HD

output

				33k
				+
	SW1		10∝ 1k2
1k		75			47p
			SW2

+5V

TTL

4k7

Fig. 6. HD and VD input.

5.3.4. HD, VD, PCLK, WEN and EEN output

Output circuit for these signals are 75 Ω

complementary emitter followers. It will TTL deliver a full TTL signal. JP5 and JP3 are for alternative configuration for pin #10.

Output level ≥4 V from 75Ω. (No termination).

The WEN polarity can be changed. Signal on pin #6/6 can be changed.

10k
220	10
	10
10k

+5V
VD, HD	SW1
67 WEN/ EEN		#6/6

JP2

PCLK #9/12

WEN #10/12

JP5 JP3

GND

Fig. 7. HD, VD, PCLK, WEN and EEN output.

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