Toshiba CS6910CL specifications Camera responds to the read request, as follows

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(2) Command Communication Protocol

The command communication protocol is the teli standard method (method in which parameters are set in the registers in the camera).

In command send/receive operation, hexadecimal address and data are converted to ASCII data. All ASCII alphabetic characters used are uppercase characters.

￿Write to a register

To write data in a register, send a command, as follows:

STX(0x02)

Addr. (upper)

Addr. (lower)

Data (upper)

Data (lower)

ETX(0x03)

For example, to write data 0x25 to address 0x75, send a command, as follows:

STX(0x02)

“7”(0x37)

“5”(0x35)

“2”(0x32)

“5”(0x35)

ETX(0x03)

The camera responds to the write command with No Error (ACK) or Error (NAK), as follows:

STX(0x02)

ACK(0x06)

ETX(0x03)

STX(0x02)

NAK(0x15)

ETX(0x03)

￿Reading the register

To read data from a register, send "R" and "Q" following the address.

For example, to read data in address 0x6D, send a command, as follows:

STX(0x02)

“6”(0x36)

“D”(0x44)

“R”(0x52)

“Q”(0x51)

ETX(0x03)

The camera responds to the read request, as follows:

STX(0x02)

Data (upper)

Data (lower)

ETX(0x03)

CCD color camera CS6910CL Specification (Rev.A) The contents described in this document may be changed without prior notice.

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D4134419A

Image 13 Contents
CCD Color Camera CS6910CL Specification Contents First Edition Date Rev. Item’05-06-07 T.Kazama Overview FeaturesComponents Camera Link I/FOptions SpecificationsCPT4000CL CCDWEN Entire area Horizontal-vertical both edge enhancement Camera Link port assignment InterfacesCable-side connector HR10A-10P-12S Hirose Pin assignment Video OUT/DC in connectorDip Switch Settings OFF Video output mode settingCamera Link Serial Control Save / Load /RESETTrigger Polarity Positive / Negative Camera responds to the read request, as follows Register Map Registers accessible to the user are as follows 0OFF Expansion This register is not used in this camera Address Function Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Sxga output timing Timing ChartsVGA TimingOutline Drawing Cases for Indemnity Limited Warranty Restriction for Use D4134419A
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