CDX-M620/M670
SECTION 4
DIAGRAMS
4-1. IC PIN DESCRIPTIONS
• IC501 CXD2598Q (DIGITAL SERVO, DIGITAL SIGNAL PROCESSOR) (SERVO BOARD)
Pin No. | Pin Name | I/O | Pin Description |
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1 | DVDD | — | Digital power supply pin |
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2 | DVSS | — | Digital ground |
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3 | SOUT | O | Servo brock serial data output (Not used.) |
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4 | SOCK | O | Servo brock serial data read clock output (Not used.) |
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5 | XOLT | O | Servo brock serial data latch output (Not used.) |
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6 | SQSO | O | Sub Q 80 bit, PCM peak and level data output. CD TEXT data output |
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7 | SQCK | I | Clock input from SQSO read out. |
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8 | SCSY | I | Fixed at “L”. |
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9 | SBSO | O | Serial output of |
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10 | EXCK | I | Clock input from SBSO read out. (Fixed at “L”) |
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11 | XRST | I | System reset (“L”: Reset) |
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12 | STSM | I | System mute input (Fixed at “L”) |
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13 | DATA | I | Serial data input from CPU. |
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14 | XLAT | I | Latch input from CPU. Latch serial data at the falling edge. |
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15 | CLOK | I | Serial data transfer clock input from CPU. |
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16 | SENS | O | SENS output for CPU. |
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17 | SCLK | I | Clock input from SENS serial data read. |
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18 | ATSK | I/O | Input/output for |
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19 | WFCK | O | WFCK (Write Flame Clock) output (Not used.) |
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20 | XUGF | O | XUGF output (Not used.) |
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21 | XPCK | O | XPCK output (Not used.) |
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22 | GFS | O | GFS output |
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23 | C2PO | O | C2PO output (Not used.) |
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24 | SCOR | O | “H” output at either detection, sub code sync S0 or S1. |
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25 | C4M | O | 4.2336 MHz output (Not used.) |
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26 | WDCK | O | Word clock output f=2Fs (Not used.) |
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27 | COUT | I/O | Track number count signal input/output (Not used.) |
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28 | MIRR | I/O | Mirror signal input/output (Not used.) |
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29 | DVSS | — | Digital ground |
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30 | DVDD | — | Digital power supply pin |
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31 | DFCT | I/O | Diffect signal input/output (Not used.) |
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32 | FOK | I/O | Focus OK signal input/output |
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33 | PWM1 | I | External control input of spindle motor. |
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34 | LOCK | I/O | Lock signal input/output |
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35 | MDP | O | Servo control output of spindle motor. |
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36 | SSTP | I | Disc most inner track detection signal input |
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37 | FSTIO | I/O | 2/3 frequency division input/output of pins ih and ij. (Not used.) |
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38 | SFDR | O | Sled drive output |
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39 | SRDR | O | Sled drive output |
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40 | TFDR | O | Tracking drive output |
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41 | TRDR | O | Tracking drive output |
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42 | FFDR | O | Focus drive output |
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43 | FRDR | O | Focus drive output |
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44 | DVDD | — | Digital power supply pin |
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45 | DVSS | — | Digital ground |
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46 | TEST | I | Test pin (Fixed at “L”.) |
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47 | TES1 | I | Test pin (Fixed at “L”.) |
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48 | XTSL | I | X’tal select input (“L”: 16.9344 MHz, “H”: 33.8688 MHz) |
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49 | VC | I | Center voltage input |
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50 | FE | I | Focus error signal input |
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51 | SE | I | Sled error signal input |
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