Xilinx UG4153 manual Running the Test Bench, Simulating the H Motion Estimation Engine Core

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Chapter 4: Simulating the H. 264 Motion Estimation Engine Core

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4.Testbench source file:

/HDL/LowCost_MotionEstimation/MotionEstimation/Testbench/ MotionEstimation_TB.vhd

Running the Test Bench

To run the test bench:

1.Double-click on the vsim_gui.bat file. This spawns the ModelSim GUI. Two wave windows are given. One (MotionEstimation_user) is meant to contain user- defined signals. The user may use this window to view any internal signals of his choice. The other (MotionEstimation_core) shows the signals at the periphery of the core to give the user a feel for the typical interfacing activity required.

If the the following error is received, the user needs to run the refresh command, vcom -refresh:

#**Error: (vsim-13) Recompile work.vfbc_infrastructure because C:\opt\Modeltech_6.1f\xilinx_libs_9_2_03i_ip2\.\unisims.vcomponents has changed.

2.In the ModelSim environment, enter run -all. This runs for about 15 minutes.

The stimulus data for this simulation is held in the

\HDL\LowCost_MotionEstimation\MotionEstimation\Testbench\stimul i directory, consisting of several input text files and some expected output text files. The stimulus data files and expected output files provided contain data extracted from the reference C model (see [Ref 1]).

The simulation generates these output files:

\HDL\LowCost_MotionEstimation\MotionEstimation\Testbench\ MotionEstimation_MVs.out.txt

\HDL\LowCost_MotionEstimation\MotionEstimation\Testbench\ MotionEstimation_ParamsMB.out.txt

\HDL\LowCost_MotionEstimation\MotionEstimation\Testbench\ MotionEstimation_SADs.out.txt

that are directly comparable to the reference expected output.

\HDL\LowCost_MotionEstimation\MotionEstimation\Testbench\ stimuli\MotionEstimation_MVs.out.txt

\HDL\LowCost_MotionEstimation\MotionEstimation\Testbench\ stimuli\MotionEstimation_ParamsMB.out.txt

\HDL\LowCost_MotionEstimation\MotionEstimation\Testbench\ stimuli\MotionEstimation_SADs.out.txt

Note: Xilinx has provided a .vho source file as an example of how to instantiate the Motion Estimation Engine core. It is not provided as compilable source code for ModelSim. All simulations are to be run using the precompiled libraries provided.

In Chapter 5, “Verifying the System,” of this document, the process by which stimulus and expected results are generated from the reference code is described. The generated files may be used in place of the default simulation files provided with the release, but must reside in the locations mentioned above during simulation.

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H.264 Motion Estimation Engine

 

 

UG453 (v1.1) April 22, 2008

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Contents Motion Estimation Engine UG453 v1.1 April 23, 2008 optionalDate Version Revision Revision History10/24/07 Initial Xilinx release 04/23/08 Table of Contents Appendix Supporting Information Schedule of Figures 1H.264 EncoderUG453 v1.1 April 23 Schedule of Tables Table A-1Regression Test SummaryMotion Estimation Engine Additional Resources Guide ContentsAbout This Guide ConventionsFile → Open Preface About This GuideMeaning or Use Example Helvetica boldConventions Hyperlink to a website URL For the latest speed filesUG453 v1.1 April 23 Recommended Design Experience IntroductionAbout the Core Additional Core ResourcesFeedback IntroductionSystem Requirements Installing the H.264 Motion Estimation Engine CoreManual Installation WindowsInstalling the H.264 Motion Estimation Engine Core NetlistsMotion Estimation in the H.264 Encoder Designing with the H.264 Motion Estimation Engine CoreVhdl Template Files Model Tech Vhdl simulator test bench codeDesigning with the H.264 Motion Estimation Engine Core 2Motion Estimation Engine Block Diagram Motion Estimation in the H.264 EncoderDesigning with the H.264 Motion Estimation Engine Core Test bench stimulus files Simulating the H Motion Estimation Engine CoreTest Bench Release ModelSim-specific script filesTestbench source file Running the Test BenchSimulating the H Motion Estimation Engine Core Simulation generates these output filesVerifying the System Verification Platform ReleaseVerification Process Level Running the Verification TestsVerifying the System Verification Notes Verification Notes…and the expected output reference file Verifying the System Directory Tree Structure Supporting InformationInput Sequences Regression Test DescriptionsReferences Figure A-1Directory Tree Structure