Xilinx UG4153 Introduction, About the Core, Recommended Design Experience, Technical Support

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Chapter 1

Introduction

This user guide is required reading for the engineer using or considering using the Xilinx® Motion Estimation Engine core. The release of this product is given in ZIP file form.

About the Core

The Xilinx Motion Estimation Engine core accepts input parameters on a frame and macroblock basis and a stream of pixels in macroblock format and generates output motion vectors, Sum-of-Absolute Difference (SAD) values, and coded block pattern with best motion vector for each block.

Recommended Design Experience

Although the Motion Estimation Engine core is a fully-verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, previous experience building high- performance pipelined FPGA designs using Xilinx implementation software and user constraints files (UCF) is recommended.

Contact your local Xilinx representative for a closer review and estimation for your specific site requirements.

Additional Core Resources

For detailed information and updates about the Motion Estimation Engine core, see the documents located on the Motion Estimation Engine product page. In general, this document should always be used in conjunction with the following:

•The Xilinx Motion Estimation Engine Product Specification (DS648)

•The MPEG4 Part 10 specification ([Ref 1])

•JM10.2 H.264 Codec Reference C Code

Technical Support

For technical support, go to www.xilinx.com/support. Questions are routed to a team of engineers with expertise using the Motion Estimation Engine core.

Xilinx provides technical support for use of this product as described in this guide.

Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines.

H.264 Motion Estimation Engine

www.xilinx.com

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UG453 (v1.1) April 23, 2008

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Contents UG453 v1.1 April 23, 2008 optional Motion Estimation EngineDate Version Revision Revision History10/24/07 Initial Xilinx release 04/23/08 Table of Contents Appendix Supporting Information 1H.264 Encoder Schedule of FiguresUG453 v1.1 April 23 Table A-1Regression Test Summary Schedule of TablesMotion Estimation Engine About This Guide Guide ContentsAdditional Resources ConventionsMeaning or Use Example Preface About This GuideFile → Open Helvetica boldHyperlink to a website URL For the latest speed files ConventionsUG453 v1.1 April 23 About the Core IntroductionRecommended Design Experience Additional Core ResourcesIntroduction FeedbackManual Installation Installing the H.264 Motion Estimation Engine CoreSystem Requirements WindowsNetlists Installing the H.264 Motion Estimation Engine CoreVhdl Template Files Designing with the H.264 Motion Estimation Engine CoreMotion Estimation in the H.264 Encoder Model Tech Vhdl simulator test bench codeDesigning with the H.264 Motion Estimation Engine Core Motion Estimation in the H.264 Encoder 2Motion Estimation Engine Block DiagramDesigning with the H.264 Motion Estimation Engine Core Test Bench Release Simulating the H Motion Estimation Engine CoreTest bench stimulus files ModelSim-specific script filesSimulating the H Motion Estimation Engine Core Running the Test BenchTestbench source file Simulation generates these output filesVerification Platform Release Verifying the SystemVerification Process Level Running the Verification TestsVerifying the System Verification Notes Verification Notes…and the expected output reference file Verifying the System Input Sequences Supporting InformationDirectory Tree Structure Regression Test DescriptionsFigure A-1Directory Tree Structure References
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