Intel Embedded Microcontroller, 8XC251SA, 8XC251SP, 8XC251SQ manual CCAP4H CCAP4L, Wdte CMOD.6 ECOM4

8XC251SA, SB, SP, SQ USER’S MANUAL

The PCA WDT generates a reset signal each time a match occurs. To hold off a PCA WDT reset, the user has three options:

•periodically change the comparison value in CCAP4H/CCAP4L so a match never occurs

•periodically change the PCA timer/counter value so a match never occurs

•disable the module 4 reset output signal by clearing the WDTE bit before a match occurs, then later re-enable it

The first two options are more reliable because the WDT is not disabled as in the third option. The second option is not recommended if other PCA modules are in use, since the five modules share a common time base. Thus, in most applications the first option is the best one.

	PCA Timer/Counter		Compare/Capture
Count			Module
Input	CH	CL	CCAP4H CCAP4L
	(8 Bits)	(8 Bits)	(8 Bits)	(8 Bits)
			16-Bit		Match			PCA WDT Reset
			Comparator
			Enable			WDTE
						CMOD.6
		X	ECOM4	0	0	1	X	0	X
		7		CCAPM4 Mode Register					0
	"0"
Reset
Write to
CCAP4L						X = Don't Care
	"1"
Write to CCAP4H
									A4165-01

Figure 9-4. PCA Watchdog Timer Mode

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