Texas Instruments TLV320AIC23, TLV320DAC23 manual Format Control, Sampling Rate Register

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Sampling Rate Register

The Apply button sends the current bit values shown on the Analog Control panel to the Audio (Format) register section of the register panel. The OK button performs the same function as the Apply button and simultaneously closes the register panel.

Figure 4–8. Format Control

4.6.11Sampling Rate Register

Address: 0001000

D7 sets the clock output divider (0 = MCLK, 1 = MCLK/2), D6 sets clock input divider (0 = MCLK, 1 = MCLK/2). D5–D2 set the SR3–SR0 bits. D1 sets the base oversampling rate (In USB mode, 0 = 250 fS and 1 = 272 fS; in normal

mode, 0 = 256 fS and 1 = 384 fS). D0 sets the USB/normal mode (0 = normal, 1 = USB).

Clicking the Clock Select button opens a Normal Clock Setup panel (see Figure 4–9) that allows the selection of master clock speed and ADC and DAC sampling rates. There are also two check boxes for setting the clock input divider and clock output divider on or off. Because the correspondence between clock settings and register bit values is not intuitively obvious, it may be easier to input the desired clock frequency and sampling rates in the Normal Clock Setup panel and observe the bit settings that appear in the registers panel. The Clock Select button in the sampling rate register box is functionally identical to the Clock Select button on the main panel (see Section 4.4.18).

The Cancel button undoes any changes that have been made in register bit values, so the register panel matches the current state of the EVM registers. The Apply button sends the current bit values shown on the Analog Control panel to the Sampling Rate register section of the register panel. The OK button performs the same function as the Apply button and simultaneously closes the register panel.

Software 4-13

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Contents User’s Guide Important Notice EVM Important Notice EVM Warnings and Restrictions Read This First How to Use This ManualAbout This Manual Related Documentation From Texas InstrumentsTrademarks Contents Figures Introduction Page Quick Start-Up Page Topic Theory of OperationTLV320AIC23 EVM2 Parts Location Diagram TLV320AIC23 EVM2 Top View Photographs of EVMTLV320AIC23 EVM2 Bottom View Parallel Port Interface Board Top View Jumper Settings TLV320AIC23 EVM2 PowerAnalog Connections Digital I/O TLV320AIC23 EVM2 FeaturesMaster Clock Digital LoopbackPage Software DASCCTAIC23 Installation AIC23/DAC23 EVM2 Connection Diagram DASCCTAIC23 Overview DASCCTAIC23 Start-UpMain Panel About ButtonHeadPhone Volume Line Input VolumeReset Button Message AreaNormal Mode and USB Mode Radio Buttons 9 I2C Adjust Button10 I2C Bypass Check Box DataLog On Check BoxI2C Adjust Clock Select ButtonFrequency Display Areas View Registers Preset ModesMode Files Vol Line Input Register 6 OK, Apply, and Cancel Buttons Vol HeadPhone Register Audio Analog RegisterAudio Digital Register Analog ControlAudio Format Register Power Down RegisterSampling Rate Register Format ControlInterface Activate Register Clock SetupDevice can be undetermined I2C Error MessagesPage Kit Contents TLV320AIC23 EVM2 Kit Contents Description Qty Part Number Mfr Ref. Des Bill of MaterialsERJ-8RQJ3R3V Circuit Card and Schematic Thu Nov 29 104853 Thu Nov 29 104627 Thu Nov 29 104713 Page
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