PIN FUNCTION DESCRIPTION
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PD<7 | I | Multiplexed Cb, Y, and Cr digital video input bus. | |||||||
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| 20 | I/O | In Slave Mode (MSTR pin is low) Horizontal Synch input. In Master | |||
HSYN | |||||||||
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| Mode (MSTR pin is high) Horizontal Synch output. | |||
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| 21 | I/O | In slave mode (MSTR pin is low) Vertical Sync input. In master mode | ||||
VSYN | |||||||||
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| Vertical Sync output. |
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MSTR | 3 | I | Master Mode; |
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| If this pin is high, the chip outputs horizontal and vertical sync signals. | |||
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| Otherwise it receives both horizontal and vertical sync signals. | |||
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CPNT | 27 | I | Select either component or composite video output. | ||||||
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| 0: Simultaneous Composite and | |||
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| 1: Component video output either RGB or YCbCr determined by the | |||
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| register CR0[5:4]. |
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PDEN | 28 | 1 | Pedestal enable pins. |
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| When this pin is high 7.5 IRE is added for the NTSC composite analog | |||
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| output. |
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CVBS | 35 | O | Analog video output |
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| Determined by the state of CPNT pin and CR0[5:4] | |||
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| CPNT CR0[5] CR0 [4] | |||
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| 0 | X | X: | Composite video output |
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| 1 | X | 0: Cr output in CbCr component mode | |
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| 1 | 0 | X: | : |
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| 1 | 1 | 1: Blue color output in RGB mode | |
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Y | 31 | O | Analog video output |
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| Determined by the state of CPNT pin and CR0[5:4] | |||
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| CPNT CR0[5] CR0 [4] | |||
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| 0 | X | X: | |
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| 1 | X | 0: Cb output in CbCr component mode | |
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| 1 | 0 | X: | : |
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| 1 | 1 | 1: | R color output in RGB mode |
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C | 33 | O | Analog video output |
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| Determined by the state of CPNT pin and CR0[5:4] | |||
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| CPNT CR0[5] CR0 [4] | |||
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| 0 | X | X: | |
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| 1 | 1 | 0: Cb output in CbCr component mode | |
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| 1 | 0 | X: | : |
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| 1 | 1 | X: Green color output in RGB mode | |
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VREF | 40 | I/O | Voltage reference. It has an internal voltage reference circuit, but may | ||||||
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| be overridden by an external voltage reference input. A 0.1 uF ceramic | |||
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| capacitor is required between this pin and GND. | |||
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IREF | 39 | I | A resistor should be connected between this pin and GND to control the | ||||||
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| DAC output current. The recommended value is 198 (382) ohm 1% | |||
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| metal film resistor for double (single) end 75 ohm termination. | |||
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COMP | 38 | I | Compensation capacitor for the DAC internal reference amplifier. A 0.1 | ||||||
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| uF ceramic capacitor is required between this pin and VDDA. | |||
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BIAS | 37 | I/O | DAC bias voltage. A 0.1 uf ceramic capacitor must be used to de- | ||||||
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| couple this pin to VDDA. |
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