Heatsink Material Considerations | HP A005 instruction

used. The S-parameter data, as presented in HP chip transistor data sheets, includes the bond wire inductance (approximately 0.7 nH per wire), microstrip line end-effect capacitance (about 0.02 pF) and microstrip line losses (about 0.1 dB). A designer modeling the chip should adjust these parasitic elements appropriately for the specific circuit configuration.

Bipolar transistor chips are characterized in a slightly different configuration because the substrate/backside of the chip is the collector and the chip is mounted on the output 50 ohm line. The emitter pad (or multiple pads, if used) is bonded to ground via holes through the alumina substrate and the base is connected to the input line. Again, bond inductances (about 0.5 nH base and 0.2 nH emitter), end-effect capacitances (about 0.02 pF) and 0.025" alumina microstrip losses (about 0.1 dB) are included in the chip data.

2.0 Heatsink Material Considerations

Although a detailed evaluation of device heatsinking is beyond the scope of this application note, some comments on the topic are in order. In general, for small signal devices the DC power dissipation levels are low enough that the heatsink material is relatively unimportant. As device dissipation levels approach 250 milliwatts and operating temperatures increase, a higher thermal conductivity material is needed for the chip mounting surface. The best choices, given fabrication constraints for a particular circuit, are gold plated copper or gold plated beryllium oxide (BeO).

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Data Subject to Change

Obsoletes 5091-8802E

5968-3242E (1/99)