HP dc7800 tower PCI Express Bus Operation, Software/Driver Layer, Transaction Protocol Layer

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System Support

The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has been granted control of the bus for the purpose of initiating a transaction. A target is a device that is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI bus (and does not already own it), the PCI device asserts its REQn signal to the PCI bus arbiter (a function of the system controller component). If the bus is available, the arbiter asserts the GNTn signal to the requesting device, which then asserts FRAME and conducts the address phase of the transaction with a target. If the PCI device already owns the bus, a request is not needed and the device can simply assert FRAME and conduct the transaction. Table 4-2 shows the grant and request signals assignments for the devices on the PCI bus.

Table 4-2.

PCI Bus Mastering Devices

Device

REQ/GNT Line

Note

 

 

 

PCI Connector Slot 1

REQ0/GNT0

[1]

 

 

 

PCI Connector Slot 2

REQ1/GNT1

[1]

 

 

 

PCI Connector Slot 3

REQ2/GNT2

[2]

 

 

 

NOTE:

[1]SFF and CMT form factors only.

[2]CMT form factor only

PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm specified by the PCI specification. The bus parking policy allows for the current PCI bus owner (excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted by another agent. Note that most CPU-to-DRAM accesses can occur concurrently with PCI traffic, therefore reducing the need for the Host/PCI bridge to compete for PCI bus ownership.

4.2.2 PCI Express Bus Operation

The PCI Express (PCIe) v1.1 bus is a high-performace extension of the legacy PCI bus specification. The PCI Express bus uses the following layers:

■Software/driver layer

■Transaction protocol layer

■Link layer

■Physical layer

Software/Driver Layer

The PCI Express bus maintains software compatibility with PCI 2.3 and earlier versions so that there is no impact on existing operating systems and drivers. During system intialization, the PCI Express bus uses the same methods of device discovery and resource allocation that legacy PCI-based operating systems and drivers are designed to use.

Transaction Protocol Layer

The transaction protocol layer processes read and write requests from the software/driver layer and generates request packets for the link layer. Each packet includes an identifier allowing any required responcse packets to be directed to the originator.

 

Technical Reference Guide

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Contents September Technical Reference GuideTechnical Reference Guide Contents Processor/Memory Subsystem System SupportInput/Output Interfaces Integrated Graphics Subsystem Power and Signal DistributionError Messages and Codes Index System BiosOnline Viewing IntroductionAbout this Guide Additional Information SourcesValues Serial NumberNotational Conventions Special NoticesCommon Acronyms and Abbreviations Acronyms and AbbreviationsAcronym or Abbreviation Description Cmos CDSCGA CMCEscd EisaEPP EideLCD IRQISA LANPCA ODDPAL PataSgram SdvoSEC SecamVAC URLUSB UTPIntroduction Introduction System OverviewFeatures Feature Difference Matrix by Form Factor Sodimm Dimm1ODD System Architecture Architectural Differences By Form FactorFunction HP Compaq dc7900 Business PC Architecture, Block diagram Intel Processor Support Chipset Chipset Components and FunctionalityComponents Function Component Name Function Support ComponentsSystem Memory Support Component FunctionsNetwork Interface Controller Mass StorageSerial Interface Universal Serial Bus InterfaceIntegrated Graphics Controller Graphics SubsystemAudio Subsystem Integrated Graphics Subsystem StatisticsParameter Operating Non-operating SpecificationsEnvironmental Specifications Factory Configuration Power Supply Electrical SpecificationsParameter Usdt SFF CMT Physical SpecificationsCD-RW/DVD-ROM Combo Optical Drive SpecificationsHP SuperMulti LightScribe ParameterParameter 80 GB 160 GB 250 GB Hard Drive SpecificationsProcessor/Memory Subsystem Architecture Processor/Memory SubsystemIntel Processor Overview Intel ProcessorsForm Processor Changing/UpgradingSupported Processors partial listing ClockMemory Subsystem Channel a Channel B Socket Socket 2 Socket 4 Total Memory UpgradingMemory Mapping and Pre-allocation Memory Socket LoadingSystem Memory Map for maximum of 8 gigabytes System Support PCI Bus OverviewPCI 2.3 Bus Operation PCI Component Function # Device # Wired to PCI Component Configuration Access PCI BusPCI Bus Mastering Devices PCI Express Bus OperationSoftware/Driver Layer Transaction Protocol LayerLink Layer PCI Power Management SupportOption ROM Mapping PCI InterruptsPCI Connectors PCI 2.3 ConnectorPCI 2.3 Bus Connector Pinout PCI Express Bus Connector Pinout PCI Express ConnectorsMode Apic ModeSystem Resources InterruptsPCI Interrupt Distribution Direct Memory AccessClearing Cmos Real-Time Clock and Configuration MemorySecurity Functions Configuration Memory Cmos MapSystem Management Standard Cmos LocationsInterface Security Power-On / Setup PasswordSetup Password Cable Lock ProvisionAcpi Wake-Up Event System Wakes From Power ManagementSmart Cover Lock Optional Acpi Wake-Up EventsSystem Operational Status LED Indications System Status PowerLED Beeps Action RequiredSystem Status Thermal Sensing and CoolingSystem I/O Map Register Map and Miscellaneous FunctionsPort Function System I/O MapGpio Functions ICH10 FunctionsSIO Controller Functions Input/Output Interfaces Pin Description Pin Sata Connector PinoutSATA/eSATA Interfaces Sata interfaceESATA interface Optional eSATA Bracket/Cable AssemblyDiskette Drive Interface Pin Signal Description Pin Diskette Drive Connector PinoutSerial Interface DB-9 Serial Connector PinoutParallel Interface Support Standard Parallel Port ModeEnhanced Parallel Port Mode Extended Capabilities Port ModeParallel Interface Connector DB-25 Parallel Connector PinoutPin Signal Function Keyboard Interface Operation Keyboard/Pointing Device InterfaceData Keyboard/Pointing Device Interface ConnectorKeyboard/Pointing Device Connector Pinout Pointing Device Interface OperationICH10 USB Port Mapping USB ConnectorController Signals USB Connector Location all form factors Universal Serial Bus InterfaceUSB Color Code USB Connector PinoutUSB Cable Data USB Cable Length DataAudio Subsystem Audio Subsystem Functional Block DiagramHD Audio Controller HD Audio Link BusAudio Multistreaming ADC/DAC Audio SpecificationsHD Audio Subsystem Specifications Parameter MeasurementLAN I/F NIC Network Interface ControllerPower Management Support Wake-On-LAN SupportAlert Standard Format Support Parameter Compatibility standard orprotocol NIC ConnectorNIC Specifications NIC SpecificationsIntegrated Graphics Subsystem RGB Functional DescriptionGMA 4500 Memory Allocation Sdram Installed Maximum Memory AllocationResolution Maximum Refresh Rate Analog Digital Monitor Display ModesIGC Standard 2D Display Modes Upgrading Monitor Connectors Analog Monitor ConnectorDB-15 Monitor Connector Pinout Pin Signal DisplayPort ConnectorIntegrated Graphics Subsystem Power and Signal Distribution Power DistributionUsdt Power Distribution Usdt 135-Watt Power Supply Unit Specifications 2 SFF/CMT Power DistributionMin Range Current Max Surge Tolerance Loading Ripple SFF 240-Watt Power Supply Unit SpecificationsRange or Min Current Max Surge Tolerance Loading Ripple CMT 365-Watt Power Supply Unit SpecificationsEnergy Star Compliancy Shows the power supply cabling for CMT systemsPressed Power Button Results Power ControlPower Button Power Button ActionsPower LED Indications Condition Wake-On-LAN Wake Up EventsConsumption To S0 by Required System Power StatesPower Transition OS Restart State System ConditionCR1 +5 VDC LED Signal DistributionSystem Board Component Designations Power and Signal Distribution System Bios ROM Flashing UpgradingChangeable Splash Screen Memory Detection and Configuration Boot FunctionsBoot Device Order Network Boot F12 SupportBoot Error Codes Boot Error CodesVisual power LED Audible speaker Meaning Function Mode Client Management FunctionsClient Management Functions INT15 Subsystem Temperature StatusSystem ID and ROM Type System ID NumbersType Data Smbios FunctionsManagement Engine Functions USB Legacy SupportBeeps Power LED Probable Cause Error Messages and CodesBeep/Power LED Codes Table A-1 Beep/Power LED CodesPower-On Self Test Post Messages Table A-2 Table A-2 Error Message Probable CauseTable A-3 System Error Messages Probable Cause System Error MessagesMessage Probable Cause Memory Error MessagesMemory Error Messages Table A-4Table A-5 Keyboard Error Messages Probable Cause Keyboard Error MessagesTable A-7 Video Graphics Error Messages Probable Cause Printer Error MessagesVideo Graphics Error Messages Table A-6 Printer Error Messages Probable CauseTable A-8 Diskette Drive Error Messages Probable Cause Diskette Drive Error MessagesTable A-9 Serial Interface Error Messages Probable Cause Serial Interface Error MessagesModem Communications Error Messages System Status Error Messages System Status Error MessagesTable A-11 Table A-12 Hard Drive Error Messages Probable Cause Hard Drive Error MessagesXx = 03, Hard drive read/write compare test Table A-13 Hard Drive Error Messages Probable Cause Audio Error Messages Table A-14 Video Graphics Error Messages Probable CauseTable A-15 Audio Error Messages Probable Cause Table A-17 Network Interface Error Messages Probable Cause 17 DVD/CD-ROM Error MessagesNetwork Interface Error Messages DVD/CD-ROM Error MessagesTable A-18 Scsi Interface Error Messages Scsi Interface Error Messages 65xx-xx, 66xx-xxPointing Device Interface Error Messages 8601-xx Error Messages and Codes Numerics IndexIndex
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dc7800 tower specifications

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