FV1:
Voltage Checkpoints Connector
These | voltage checkpoint | are | used | to | measure | the current system volt- | |||||||||
ages. | A | multimeter | (not | included) | will | be | required to | check | voltages. | To | |||||
check | the | voltage, | please | use | the | included | voltage | checkpoint | cables includ- | ||||||
ed | in | the mainboard package. Attach the positive | lead | of | the | multimeter | to | ||||||||
the | voltage checkpoint cable and the | negative lead | to the | ground connector. | |||||||||||
|
|
|
|
|
|
|
|
|
| 7 | GND |
|
|
| |
|
|
|
|
|
|
|
|
|
|
| PCH_1P1V |
|
| ||
|
|
|
|
|
|
|
|
|
|
| DDR C/ D |
|
| ||
|
|
|
|
|
|
|
|
|
|
| DDR A/ B |
|
| ||
|
|
|
|
|
|
|
|
|
|
| CPU_SA |
|
|
| |
|
|
|
|
|
|
|
|
|
|
| CPU_IO |
|
|
| |
|
|
|
|
|
|
|
|
|
| 1 | CPU_CORE |
|
| ||
Chapter 1
Point | Description |
|
|
GND (pin 7) | Ground |
|
|
PCH_1P1V (pin 6) | PCH 1.1 voltage. The PCH voltage is the voltage supplied to |
| the platform Controller Hub. |
DDR_C/D (pin 5) | Memory channel C and D voltage. The DDR memory voltage |
| is the voltage supplied to the DDR memory modules on |
| the mainboard. Lower memory timings may require higher |
| voltages to maintain system stability. |
DDR_A/B (pin 4) | Memory channel A and B voltage. Refer to rhe DDR_C/D. |
|
|
CPU_SA (pin 3) | CPU system agent voltage (iMC). The CPU SA voltage is the |
| voltage supplied to the iMC (integrated Memory Controller) |
| on the CPU. Higher overclocks may require a higher CPU |
| SA voltage to maintain stability. |
CPU_IO (pin 2) | CPU IO voltage (Uncore). The CPU IO voltage is the voltage |
| supplied to the Uncore on the CPU. Higher overclocks may |
| require a higher CPU IO voltage to maintain stability. |
CPU_CORE (pin 1) | CPU core voltage. The CPU voltage is the voltage suppoied |
| to the CPU core. Higher overclocks may require higher CPU |
| core voltages to maintain stability. |