Toshiba SR-C8002 specifications 14/24, Shows the Host Interface Timings

6.2.2.Timing of Host Interface (PIO)

Figure 9 shows the Host Interface Timings

Address valid*1

t2 t1

DIOR-/DIOW-*1

Write data valid*1

Read data valid*1

t7

IOCS16-*1

tA tB

IORDY

t0

t9

t2i

t3

t4

t5 t6Z

t6

t8 tRD

*1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted.

	PIO timing parameters min (ns) max (ns)	Min Time (ns)	Max Time (ns)
t0	Cycle time	120
t1	Address valid to DIOR/DIOW-setup	25
t2	DIOR/DIOW-pulse wide	70
t2i	DIOR/DIOW-recovery time	25
t3	DIOW-data setup	20
t4	DIOW-data hold	10
t5	DIOR-data setup	20
t6	DIOR-data hold	5
t6Z	DIOR-data tristate		30
t7	Addr valid to IOCS 16-assertion		30
t8	Addr valid to IOCS 16-negation		30
t9	DIOR/DIOW-to address valid hold	10
tRD	Read Data Valid to IORDY active	0
tA	IORDY setup		35
tB	IORDY pulse wide		1250

Figure 9 Host Interface Timing (PIO Mode4)

14/24 SR-C8002 Rev.1.0