ELAN Home Systems EM78P459AK manuals

60 pages2.15 Mb

EM78P458/459
- 2Specification Revision History Version Content
- Application Note
- 31. GENERAL DESCRIPTION
- 4EM78P458/459
  - 2. FEATURES
- 5EM78P458/459
  - 63. PIN ASSIGNMENT
- 8EM78P458/459
  - OTP ROM
    - RAM
    - ALU
  - 4. FUNCTION DESCRIPTION
    - IOC5 R5
    - IOC6 R6
    - ROM
    - /INT
    - R1(TCC)
    - Fig. 2 The Functional Block Diagram of EM78P458/459
    - 4.1 Operational Registers
      - 1. R0 (Indirect Addressing Register)
      - 2. R1 (Time Clock /Counter)
      - 3. R2 (Program Counter) & Stack
- 9EM78P458/459
  - 104. R3 (Status Register)
  - 5. R4 (RAM Select Register)
  - 6. R5 ~ R6 (Port 5 ~ Port 6)
  - 7. R7 ~ R8
    - 11 Fig. 4 Data Memory Configuration
  - 128. R9 (ADCON: Analog to Digital Control)
  - 9. RA (ADDATA: the converted value of ADC)
  - 10. RB
  - 11. RC
  - 12. RD
  - 13OTP ROM
    - 13. RE
    - 14. RF (Interrupt Status Register)
    - 15. R10 ~ R3F
  - 4.2 Special Purpose Registers
    - 1. A (Accumulator)
    - 142. CONT (Control Register)
    - 3. IOC50 ~ IOC60 (I/O Port Control Register)
    - 154. IOC90 (GCON: I/O Configuration & Control of ADC )
    - 5. IOCA0 ( AD-CMPCON ):
    - 166. IOCB0 (Pull-down Control Register)
    - 177. IOCC0 (Open-Drain Control Register)
    - 8. IOCD0 (Pull-high Control Register)
    - 189. IOCE0 (WDT Control Register)
    - 10. IOCF0 (Interrupt Mask Register)
    - 1911. IOC51 ( PWMCON ):
  - 22OTP ROM 4.3 TCC/WDT & Prescaler
  - 23OTP ROM
    - 8-bit Counter 8-to-1 MUX
    - Fig. 5 Block Diagram of TCC and WDT
  - 4.4 I/O Ports
    - - M U X
        PORT
        PDWR
        PCWR
        PDRD
        INT
        D
        PDWR
        PCWR
      - IOD
        PDRD 0 1
        PCRD
        D
      - _ _
        C L
        P R
        CLK
    - 24NOTE: Pull-down is not shown in the figure.
      - Fig. 6 The Ccircuit of I/O Port and I/O Control Register for Port 5
        PCRD
        M U X
        IOD
        0 1
        P50, /INT Bit 6 of IOCE0
        PORT
        TI 0
    - NOTE: Pull-high (down) and Open-drain are not shown in the figure.
      - Fig. 7 The Circuit of I/O Port and I/O Control Register for P50(/INT)
    - 25NOTE: Pull-high (down) and Open-drain are not shown in the figure.
      - Fig. 8 The Circuit of I/O Port and I/O Control Register for P60~P67
      - Fig. 9 Block Diagram of Port 6 with Input Changed Interrupt/Wake-up
  - 26OTP ROM
  - 4.5 RESET and Wake-up
    - 1. The function of RESET and Wake-up
    - 282. The Status of T, and P of STATUS Register
  - 30OTP ROM 4.6 Interrupt
  - 31OTP ROM
  - 4.7 Analog-To-Digital Converter (ADC)
    - 321. ADC Control Register (ADCON/R9, AD-CMP-CON/IOCA0, GCON/IOC90)
    - 332. ADC Data Register (ADDATA/RA)
    - 343. A/D Sampling Time
    - 4. A/D Conversion Time
    - 5. A/D Operation During Sleep Mode
    - 6. Programming Steps/Considerations
  - 37OTP ROM
  - 4.8 Dual Sets of PWM ( Pulse Width Modulation )
    - 1. Overview
      - Fig. 13 The Functional Block Diagram of the Dual PWMs
        Period Duty Cycle DT1 = TMR1
        PRD1 = TMR1
      - Fig. 14 The Output Timing of the PWM
    - 382. Increment Timer Counter ( TMRX: TMR1H/TWR1L or TMR2H/TWR2L )
    - 393. PWM Period ( PRDX : PRD1 or PRD2 )
    - 4. PWM Duty Cycle ( DTX: DT1H/ DT1L and DT2H/ DT2L; DTL: DL1H/DL1L and DL2H/DL2L )
    - 5. Comparator X
    - 6. PWM Programming Procedures/Steps
  - 40OTP ROM 4.9 Timer
    - 1. Overview
    - 2. Function description
  - 41OTP ROM
  - 4.10 Comparator
    - 423. Using as An Operation Amplifier
    - 4. Interrupt
    - 5. Wake-up from SLEEP Mode
  - 43OTP ROM
  - 4.11 The Initialized Values after Reset
    - Table 11 The Summary of the Initialized Values for Registers
- 45EM78P458/459
  - OTP ROM
    - X: not used. U: unknown or dont care. P: previous value before reset. t: check Table 5
  - 4.12 Oscillator
    - 1. Oscillator Modes
    - 462. Crystal Oscillator/Ceramic Resonators (XTAL)
    - 483. External RC Oscillator Mode
    - 494. RC Oscillator Mode with Internal Capacitor
  - 50OTP ROM 4.13 Power-on Considerations
    - 1. External Power on Reset Circuit
    - 2. Residue-Voltage Protection
  - 51OTP ROM
  - 4.14 CODE OPTION
    - 1. Code Option Register (Word 0)
    - 522. Code Option Register (Word 1)
  - 53OTP ROM 4.15 Instruction Set
    - 54
  - 55OTP ROM 4.16 Timing Diagrams
    - RESET Timing (CLK="0")
    - TCC Input Timing (CLKS="0")
    - AC Test Input/Output Waveform
  - OTP ROM
  - 576. ELECTRICAL CHARACTERISTICS
    - 6.1 DC Electrical Characteristic(Ta=0C ~ 70 C, VDD=5.0V5%, VSS=0V)
- 58EM78P458/459
  - OTP ROM 6.2 AC Electrical Characteristic(Ta=0C ~ 70 C, VDD=5V5%, VSS=0V)
    - *N= selected prescaler ratio.
  - 6.3 A/D Converter Characteristic
  - 6.4 Comparator(OP) Characteristic(Vdd = 5.0V,Vss=0V,Ta=0 to 70)
- 59EM78P458/459
  - 60APPENDIX