ELAN Home Systems EM78P458, EM78P458AM, EM78P458AP, EM78P459, EM78P459AK, EM78P459AM 6. IOCB0 (Pull-down Control Register)

EM78P458/459

OTP ROM

1 = The Vref of the ADC is connected to P53/VREF.

• Bit 6 (CE): Comparator enable bit

0 = Comparator is off (default value);

1 = Comparator is on.

• Bit 5 ( COE ): Set P57 as the output of the comparator

0 = the comparator acts as an OP if CE=1.

1 = act as a comparator if CE=1.

• Bit4:Bit2 (IMS2:IMS0):

Input Mode Select. ADC configuration definition bit. The following Table describes how to define the

characteristic of each pin of R6.

Table 3 Description of AD Configuration Control Bits

IMS2:IMS0 P60 P61 P62 P63 P64 P65 P66 P67

000 A D D D D D D D

001 A A D D D D D D

010 A A A D D D D D

011 A A A A D D D D

100 A A A A A D D D

101 A A A A A A D D

110 A A A A A A A D

111 A A A A A A A A

• Bit 1: Bit 0 (CKR1: CKR0): The prescaler of oscillator clock rate of ADC

00 = 1: 4 (default value);

01 = 1: 16;

10 = 1: 64;

11 = The oscillator clock source of ADC is from WDT ring oscillator frequency.

( frequency=256/18ms≒14.2Khz)

6. IOCB0 (Pull-down Control Register)

7 6 5 4 3 2 1 0

/PD7 /PD6 /PD5 /PD4 /PD3 /PD2 /PD1 /PD0

• Bit 0 (/PD0) Control bit is used to enable the pull-down of the P60 pin.

0: Enable internal pull-down;

1: Disable internal pull-down.

• Bit 1 (/PD1) Control bit is used to enable the pull-down of the P61 pin.

• Bit 2 (/PD2) Control bit is used to enable the pull-down of the P62 pin.

• Bit 3 (/PD3) Control bit is used to enable the pull-down of the P63 pin.

This specification is subject to change without prior notice. 07.01.2003 (V1.3)

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Contents

Main EM78P458/459 Specification Revision History Version Content Application Note 1. GENERAL DESCRIPTION EM78P458/459 2. FEATURES EM78P458/459 3. PIN ASSIGNMENT Page EM78P458/459 OTP ROM RAM ALU 4. FUNCTION DESCRIPTION EM78P458/459 4. R3 (Status Register) 5. R4 (RAM Select Register) 6. R5 ~ R6 (Port 5 ~ Port 6) 7. R7 ~ R8 Fig. 4 Data Memory Configuration 8. R9 (ADCON: Analog to Digital Control) 9. RA (ADDATA: the converted value of ADC) 10. RB 11. RC 12. RD OTP ROM 13. RE 14. RF (Interrupt Status Register) 15. R10 ~ R3F 4.2 Special Purpose Registers 2. CONT (Control Register) 3. IOC50 ~ IOC60 (I/O Port Control Register) 4. IOC90 (GCON: I/O Configuration & Control of ADC ) 5. IOCA0 ( AD-CMPCON ): 6. IOCB0 (Pull-down Control Register) 7. IOCC0 (Open-Drain Control Register) 8. IOCD0 (Pull-high Control Register) 9. IOCE0 (WDT Control Register) 10. IOCF0 (Interrupt Mask Register) 11. IOC51 ( PWMCON ): Page Page OTP ROM 4.3 TCC/WDT & Prescaler OTP ROM 8-bit Counter 8-to-1 MUX Fig. 5 Block Diagram of TCC and WDT 4.4 I/O Ports NOTE: Pull-down is not shown in the figure. Fig. 6 The Ccircuit of I/O Port and I/O Control Register for Port 5 PCRD M U X IOD NOTE: Pull-high (down) and Open-drain are not shown in the figure. Fig. 8 The Circuit of I/O Port and I/O Control Register for P60~P67 Fig. 9 Block Diagram of Port 6 with Input Changed Interrupt/Wake-up OTP ROM 4.5 RESET and Wake-up 1. The function of RESET and Wake-up Page 2. The Status of T, and P of STATUS Register Page OTP ROM 4.6 Interrupt OTP ROM 4.7 Analog-To-Digital Converter (ADC) 1. ADC Control Register (ADCON/R9, AD-CMP-CON/IOCA0, GCON/IOC90) 2. ADC Data Register (ADDATA/RA) 3. A/D Sampling Time 4. A/D Conversion Time 5. A/D Operation During Sleep Mode 6. Programming Steps/Considerations Page Page OTP ROM 4.8 Dual Sets of PWM ( Pulse Width Modulation ) 1. Overview Fig. 13 The Functional Block Diagram of the Dual PWMs Period Duty Cycle DT1 = TMR1 2. Increment Timer Counter ( TMRX: TMR1H/TWR1L or TMR2H/TWR2L ) 3. PWM Period ( PRDX : PRD1 or PRD2 ) 4. PWM Duty Cycle ( DTX: DT1H/ DT1L and DT2H/ DT2L; DTL: DL1H/DL1L and DL2H/DL2L ) 5. Comparator X 6. PWM Programming Procedures/Steps OTP ROM 4.9 Timer 1. Overview 2. Function description OTP ROM 4.10 Comparator 3. Using as An Operation Amplifier 4. Interrupt 5. Wake-up from SLEEP Mode OTP ROM 4.11 The Initialized Values after Reset Table 11 The Summary of the Initialized Values for Registers Page EM78P458/459 OTP ROM X: not used. U: unknown or dont care. P: previous value before reset. t: check Table 5 4.12 Oscillator 1. Oscillator Modes 2. Crystal Oscillator/Ceramic Resonators (XTAL) Page 3. External RC Oscillator Mode 4. RC Oscillator Mode with Internal Capacitor OTP ROM 4.13 Power-on Considerations 1. External Power on Reset Circuit 2. Residue-Voltage Protection OTP ROM 4.14 CODE OPTION 1. Code Option Register (Word 0) 2. Code Option Register (Word 1) OTP ROM 4.15 Instruction Set OTP ROM 4.16 Timing Diagrams RESET Timing (CLK="0") TCC Input Timing (CLKS="0") AC Test Input/Output Waveform Page OTP ROM 6. ELECTRICAL CHARACTERISTICS 6.1 DC Electrical Characteristic(Ta=0C ~ 70 C, VDD=5.0V5%, VSS=0V) EM78P458/459 OTP ROM 6.2 AC Electrical Characteristic(Ta=0C ~ 70 C, VDD=5V5%, VSS=0V) *N= selected prescaler ratio. 6.3 A/D Converter Characteristic 6.4 Comparator(OP) Characteristic(Vdd = 5.0V,Vss=0V,Ta=0 to 70) EM78P458/459 APPENDIX