EM78P458/459

OTP ROM

4. FUNCTION DESCRIPTION

DATA & CONTROL BUS
IOC5R5
P
5
0
P
5
1
P
5
2
P
5
3
P
5
4
P
5
5
P
5
6
P
5
7
Comparators 8ADC2PWMs
IOC6R6
P
6
0
P
6
1
P
6
2
P
6
3
P
6
4
P
6
5
P
6
6
P
6
7
ACCR3
STACK 0
STACK 1
STACK 2
STACK 3
STACK 4
P C
ROM
Instruction
Register
Instruction
Decoder
ALU
Interrupt
Control
/INT
R4
RAM
WDT Timer
Prescaler
Oscillator/
Timming
Control
WDT
Time-out
R1(TCC)
Sleep
&
Wake Up
Control
ENTCC
STACK 5
STACK 6
STACK 7
Fig. 2 The Functional Block Diagram of EM78P458/459

4.1 Operational Registers

1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect addressing
pointer. Any instruction using R0 as a pointer, actually accesses data pointed by the RAM Select
Register (R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge through the TCC pin, or by the instruction cycle clock.
• The signals to increase the counter are decided by Bit 4 and Bit 5 of the CONT register.
• Writable and readable as any other registers.
3. R2 (Program Counter) & Stack
• R2 and hardware stacks are 12-bit wide. The structure is depicted in Fig. 4.
• Generates 4K×13 bits on-chip ROM addresses to the relative programming instruction codes. One
program page is 1024 words long.
This specification is subject to change without prior notice. 07.01.2003 (V1.3)
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