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Lucent Technologies MN10285K User Manual
338 pages 5.85 Mb
4 Contents10 List of Tables12 List of Figures26 (7 machine cycles Max. 6 machine cycles Interrupt 25 ()Nonmaskable Interrupt Receive Reset Receive Maskable Interrupt Receive CPU Core )Figure 1-7 Interrupt Servicing SequenceHardware processingPush PC, PSW Main program x'080008' Interrupt service routine Header resets interrupt vector Interrupt preprocessingPush registers, branch to entry address, etc. JMP, etc. General Specifications 26 27 1.4 General Sp ecificationsTable 1-1 General Specifications Parameter Specification 28 General Specifications27 Table 1-1 General Specifications Parameter Specification 28 29 1.5 Block DiagramFigure 1-8 Functional Block Diagram 30 29Table 1-2 Block Diagram Explanation Block Description 30 31 1.6 Pin Descriptions1.6.1 MN102H85K Pin Description 32 1.6.2 MN102H75K Pin Description84-Pin QFP Top View 33 32Table 1-3 Pin Functions Block Pin Name I/O Pin Count Description 34 33Table 1-3 Pin Functions (Continued) Block Pin Name I/O Pin Count Description 35 Bus Interface 35 36 1.7 Bus Interface38 2 Interrupts73 3 Low-Power Modes78 4TimersTM3UDIR TM0O TM3 TM1 TM0 TM2 timer Clock output 4.1 8-Bit Timer DescriptionFigure 4-1 Timer Configuration Examples Note: BOSC = 24 MHz Figure 4-2 Block Diagram of 8-Bit Timers Cascading Connections 8-bit x 4 16-bit 8-bit 8-bit 8-bit 8-bit 16-bitInterval timer Sync. transfer clock UART transfer clock Event timer Event Configuration exampleTM0UDIR TM1UDIR TM2UDIR TM1I TM1O 8-Bit Timer Features 78 79 4.2 8-Bit Timer FeaturesTable 4-1 8-Bit Timer Functions and Features Function/Feature Timer 0 Timer 1 Timer 2 Timer 3 8-Bit Timer Block Diagrams 79 80 4.3 8-Bit Timer Block DiagramsReload Figure 4-3 Timer 0 Block Diagram Figure 4-4 Timer 1 Block Diagram 81 8-Bit Timer Block Diagrams80 Figure 4-5 Timer 2 Block Diagram Figure 4-6 Timer 3 Block Diagram 82 4.4 8-Bit Timer Timing83 4.5 8-Bit Timer Setup Examples4.5.1 Setting Up an Event Counter Using Timer 084 83TM0UDICL (example) x00FC74 TM0UDICH (example) x00FC75 TM0BR (example) x00FE 10 Figure 4-10 Event Counter Timing (Timer 0)Interrupt enable TM0BR TM0BCTimer 0 underflow interrupt TM0IO (2) (4) (5) (3) (6) TM0BR(B) TM0MD(B) TM0UDICH(B) TM0MD(B) 00 03 00 03 02 01 00 03 Sequence 85 4.5.2 Setting Up an Interval Timer Using Timers 1 and 286 85TM2UDICH (example) x00FC71 TM1MD (example) x00FE21 TM2UDICL (example) x00FC70 TM1UDICH (example) x00FC73 TM1UDICL (example) x00FC72 TM1BR (example) x00FE 11 TM2BR (example) x00FE 12 87 86TM2MD (example) x00FE22 Figure 4-13 Interval Timer Timing (Timers 1 and 2) 8-Bit Timer Control Registers 87 88 4.6 8-Bit Timer Control RegistersTM0BCTM3BC: Timer n Binar y Counter x00FE00x00FE03 TM0BRTM3BR: Timer n Base Register x00FE10x00FE13 TM0MDTM3MD: Timer n Mode Register x00FE20x00FE23 TMnEN: TMnBC count enable 0: Disable / 1: EnableTMnLD: TMnBR value load to TMnBC 0: Do not load value / 1: Load valueTMnS[1:0]: Timer n clock source select Table 4-2 8-Bit Timer Control Registers Register Address R/W Description 89 4.7 16-Bit Timer Description90 4.8 16-Bit Timer FeaturesTable 4-3 16-Bit Timer Functions and Features Function/Feature Timer 4 Timer 5 16-Bit Timer Block Diagrams 90 91 4.9 16-Bit Timer Block Diagrams4.10 16-Bit Timer TimingFigure 4-15 Timer 4 Block Diagram Figure 4-16 Timer 5 Block Diagram Figure 4-17 Single-Phase PWM Output Timing (16-Bit Timers) CA TMnIOA TMnOA BC value 95 4.11 16-Bit Timer Setup Examples126 4.12 16-Bit Timer Control RegistersTM4CB/TM5CB: Timer n Compare/Capture Register B x00FE88/x00FE98 TM4BC/TM5BC: Timer n Binary Counter x00FE82/x00FE92TMnCA and TMnCB are 16-bit access registers. Use the MOV instruction to write to them. TM4CA/TM5CA: Timer n Compare/Capture Register A x00FE84/x00FE94 Table 4-6 16-Bit Timer Control Registers Register Address R/W Description 127 128 5 Serial InterfacesFigure 5-1 Serial Interface Configuration Example 5.1 Description 5.2 FeaturesConnecting the Serial Interfaces 128 129 5.3 Connecting the Serial InterfacesFigures 5-2, 5-3, and 5-4 illustrate six different methods of connecting the serial interface. 5.3.1 Synchronous Serial Mode Connections 5.3.2 UART Mode ConnectionsFigure 5-3 shows serial port connections for either simplex or full-duplex UART transfers. 5.3.3 I2C Mode ConnectionFigure 5-2 Synchronous Serial Mode Connections Figure 5-3 UART Mode Connections Figure 5-4 I2C Mode Connection SBO SBTMaster Slave MN102H75K Slave 130 5.4 UART Mode Baud RatesIn these timing charts, the character length is 8 bits and there is parity. 5.5 Serial Inte rface Timing 132 5.6 Serial Inte rface Setup Example s141 5.7 Serial Interf ace Control Registers144 6 Analog-to-Digital Converter154 7 On-Screen Display7.1 Description 7.2 FeaturesTable 7-1 OSD Functions and Features Function/Feature Text Layer Graphics Layer 154 155 7.3 Block DiagramPolarity switch Figure 7-1 OSD Block Diagram 156 7.4 Power-Saving Considerations in the OSD Block157 7.5 OSD Operation160 7.6 Standard and Extended Display Modes162 7.7 Display Setup Examples7.7.1 Setting Up the Graphics LayerTable 7-5 Example Graphics VRAM Settings Line No. RAM Addr. RAM Data Data Type Description 163 162Figure 7-4 Graphics Display Example 163 164 7.7.2 Setting Up the Text LayerTable 7-6 Example Text VRAM Settings Line No. RAM Addr. RAM Data Data Type Description 165 164Figure 7-5 Text Display Example 165 166 7.8 VRAM7.8.1 VRAM OperationCC: Character Code ID Code: 00 CCH[9:0] Specifies the address of one of 1024 characters stored in the ROM.COL: Color Control Code (Normal Mode) ID Code: 10 BSHAD[1:0] CSHAD Specifies character shadowing for a 3D effect. 0: Disable 1: Enable Specifies character outlining (black). 0: Disable 1: EnableTable 7-7 VRAM Bit Allocation in Internal RAM Text l ayer Graphics layer 169 170 7.8.2 VRAM OrganizationText RAM Addresses Graphics RAM Addresses Program Data and Stack Area Graphics VRAM Text VRAM 171 170Figure 7-7 Graphics VRAM Organization for Two Modes 172 7.8.3 Cautions about the number of display code set to VRAM173 7.9 ROM7.9.1 ROM OrganizationText ROM AddressesEach character requires 36 bytes. Program Data Area Text ROM Text character Graphics tile (16-color mode) Graphics ROM AddressesIn 16-color mode, each tile requires 128 bytes. Graphics ROM 173 174 7.9.2 Graphics ROM Organization in Different Color ModesLine 16 Use graphics palette 6 Use graphics palette 5 Use graphics palette 4 Use graphics palette 3 Use graphics palette 2 Use graphics palette 1 Use graphics palette 0 Figure 7-10 Graphics ROM Setup Example for a Single LineLine 1 data Line 2 data Line 3 data Line 15 data Line 16 data 8 bytes Graphics tile(16-color mode) (16-color mode) 1010 1010 1100 1100 1111 0000(Setup example)Use graphics palette 7 Graphics tileLine 1 Line 2 Line 3 In this example, line 16 of the code 00 graphics tile is set in 16-color mode. 174 Figure 7-11 Graphics ROM in the Four Color Modes (16W x 16H Tiles)2 colors See fig.7-12 See fig.7-14 See fig.7-13 See fig.7-15 32 bytes 175 Graphic Tile Codes8 colors 96 bytes 64 bytes 128 bytes175 Figure 7-12 Graphics ROM in the Four Color Modes (16W x 18H Tiles)2 colors See fig.7-16 See fig.7-18 See fig.7-17 See fig.7-19 36 bytes 176 Graphic Tile Codes8 colors 108 bytes 72 bytes 144 bytes177 176Line 16 data 8 bytes 32 bytesLine 16 data 2 bytes Line 16 data 4 bytes Line 16 data 6 bytes Figure 7-13 Graphics ROM Organization in 16-Color Mode (16W x 16H Tiles) Figure 7-14 Graphics ROM Organization in 8-Color Mode (16W x 16H Tiles) Figure 7-15 Graphics ROM Organization in 4-Color Mode (16W x 16H Tiles) Figure 7-16 Graphics ROM Organization in 2-Color Mode (16W x 16H Tiles)128 bytes 96 bytes 64 bytes 178 177Line 18 data 8 bytes 36 bytesLine 18 data 2 bytes Line 18 data 4 bytes Line 18 data 6 bytes Figure 7-17 Graphics ROM Organization in 16-Color Mode (16W x 18H Tiles) Figure 7-18 Graphics ROM Organization in 8-Color Mode (16W x 18H Tiles) Figure 7-19 Graphics ROM Organization in 4-Color Mode (16W x 18H Tiles) Figure 7-20 Graphics ROM Organization in 2-Color Mode (16W x 18H Tiles)144 bytes 108 bytes 72 bytes 179 7.10 Setting Up t he OSD7.10.1 Setting Up the OSD Display Colors 184 Internal DAC200 ABCDE CDE ABCDE7.13.4 Controlling Line Shuttering 201 ABCDE202 7.14 Field Detection Circuit204 7.15 OSD RegistersA17 A8 All registers in OSD block cannot be written by byte (by word only). Read by byte is possible.CROMEND: Text ROM End Address Register x007F00 GROMEND: Graphics ROM End Address Register x007F02 RAMEND: Text and Graphics RAM End Address Register x007F04 0000 10XX XXXX XXXX 1111 1111 0000 1000 0000 0000 1111 1111 0000 1011 1111 1111 1111 1111 0800FF 0BFFFF 206 0: Graphics color palette 1 1: Graphics color palette 2Use the same ROM data as that used for the graphics. 214 213CPT0CPTF: Text Palette Colors 015 Registers x007F80x007F9E 215 214BBSHD: Black Box Shadowing Register x007FA4 217 8 IR Remote Signal Receiver228 9 Closed-Caption Decoder9.1 Description 9.2 Block Diagram 229 9.3 Functional DescriptionCLH VREFLS 1 F (Used as P33) VREFLS 9.3.1 Analog-to-Digital ConverterFigure 9-2 Recommended ADC Configuration Figure 9-3 External Connection with Both CCD0 and CCD1 Unused Figure 9-4 External Connection with Only CCD1 UnusedClamping circuit VREFHS CVBS0 CVBS1 CLH CLL+ VIDEO IN VREFHS CVBS0 CVBS1 External circuit 33 k 6.8 k CLL 229 230 9.3.2 Clamping CircuitA/D This block clamps the input video signal (CVBS0, CVBS1). Table 9-2 Caption decoder register setting VBI control ADC control Clamp control Figure 9-5 Clamping Circuit Table 9-3 Clamping Reference and Compare Levels Clamping Type Reference Level Compare Level CCD0 CCD1 CCD0 CCD1 231 9.3.3 Sync Separator Circuit232 231Figure 9-6 Sync Separator Circuit Block Diagram 234 9.3.4 Data Slicer235 9.3.5 Controller and Sampling Circuit237 9.4 Closed-Caption Decoder RegistersAddress CCD1 Table 9-9 Closed-Caption Decoder Register Register CCD0 Address R/W Description 239 HNUM: HSYNC Count Register x007E06 (HNUMW x007E26) VBIIRQ[4:0]: VBI interrupt timing control SBFLAG: Start bit detection fla g 240 0: No start bit detected 1: Start bit detectedHNUM[4:0]: HSYNC count during the VBI interval This field indicates the H line number, from 0 to 25.For designs using the closed-cap- tion decoder, always tie the ACQ1 register to x1312. ACQ1: ACQ Capture Timing Control Register 1 x007E08 (ACQ1W x007E28) ACQ1E[4:0]: Stop position for ACQ capture 1 Valid range: x00 to x25ACQ1S[4:0]: Start position for ACQ capture 1 Valid range: x00 to x25CAPDATA: C a ption Data Capture Register x007E0A (CAPDATAW x007E2A) CAPDA[15:0]: Caption data This register stores the 16-bit captured caption data.240 CRIFA: CRI Frequency Width Register A x007E0C (CRIFAW x007E2C) CRI2FQW[7:0]: CRI frequency width 2 241 This field indicates the width, in clock units, from the second to the third CRI1FQW[7:0]: CRI frequency width 1 This field indicates the width, in clock units, from the first to the second CRIFB: CRI Frequency Width Register B x007E0E (CRIFBW x007E2E) CRI4FQW[7:0]: CRI frequency width 4 CRI3FQW[7:0]: CRI frequency width 3 This field indicates the width, in clock units, from the third to the fourth CRI1S: CRI Capture Start Timing Control Register 1 x007E10 (CRI1SW x007E30) CRI1S[10:0]: Start position for CRI capture 1 241 CRI1E: CRI Capture Stop Timing Control Register 1 x007E12 (CRI1EW x007E32) CRI1E[10:0]: Stop position for CRI capture 1 CRI2S: CRI Capture Start Timing Control Register 2 x007E14 (CRI2SW x007E34) CRI2S[10:0]: Start position for CRI capture 2 CRI2E: CRI Capture Stop Timing Control Register 2 x007E16 (CRI2EW x007E36) CRI2E[10:0]: Stop position for CRI capture 2 242 Set this field so that the last CRI rising edge is included. The valid range is x000 to x7FF.DATAS: Data Capture Start Timing Control Register x007E18 (DATASW x007E38) DATAS[10:0]: Start position for data capture 242 DATAE: Data Capture Stop Timing Control Register x007E1A (DATAEW x007E3A) DATAE[10:0]: Stop position for data capture STAP: Sampling Start Position Register (Software Setting) x 007E1C (STAPW x007E3C) MING: Output select for noise filter detecting minimum sync tip 243 0: Low-pass filter 1 1: Low-pass filter 2, 3, or 4 (set in NFSW[1:0])NFSW[1:0]: Noise filter switch (for composite sync separator) 243 FQSEL: Frequency Select Register x007EC2 (FQSELW x007EE2) VFQDIV[5:0]: Sampling frequency setting for VSYNC separator 244 In this field, set the ratio by which to divide the sampling frequency for the HSYNC separator.FQDIV[3:0]: Sampling frequency setting for HSYNC separator In this field, set the ratio by which to divide the A/D sampling frequency.SCMING: Minimum Sync Level Detection Interval Set Register x007EC4 (SCMINGW x007EE4) SCMING[9:0]: Interval setting for the minimum sync level detection BPPST: Backporch Position Register x007EC6 (BPPSTW x007EE6) BPPST[8:0]: Backporch start position for the leading edge of HSYNC 246 HSEP1: HSYNC Separator Control Register 1 x007ECE (HSEP1W x007EEE) HSFREQ[10:0]: Correction HSYNC frequency HSEP2: HSYNC Separator Control Register 2 x007ED0 (HSEP2E x007EF0) HCLOSEE[9:0]: Start position for HSYNC detection FIELD: Field Detection Control Register x007ED2 (FIELDW x007EF2) ODDEVEN: Field detection signal 247 0: Odd field 1: Even fieldVPHASE[9:0]: Phase difference setting for VSYNC and HSYNC HLOCKLV: Sync Separator Detection Control Register 1 x007ED4 (HLOCKLVW x007EF4) HLOCKLV[8:0]: Sync separator detection threshold 248 0: 0H to 127H VSYNC separation mask 1: No maskUse this register to monitor the status of the sync separator. 0: Asynchronous 1: Synchronous 250 10 Pulse Width Modulator252 11 I/O Ports11.1 Description 253 11.2 I/O Port Circuit Diagrams258 257Figure 11-6 /PWM2 (Port 1), P20/PWM3, P21/PWM4, P22/PWM5, and P23/PWM6 (Port 2) 258 Figure 11-7 P24/TM4IC/SBT1 (Port 2) 259 To use as SBT1,set P2MD8 and P2MD9 to 0. 261 260Figure 11-9 P35/DAROUT/R, P36/DAGOUT/G, P37/DABOUT/B (Port 3), and P40/DAYMOUT/YM (Port 4) 262 261Figure 11-10 P25/TM4IOB/SBI1/SBD1 and P26/TM4IOA/SBO1 (Port 2) 263 262Figure 11-11 P55 and P56 (Port 5) 265 264Figure 11-13 P02/SCL1 (Port 0) and P61/SCL0 (Port 6) 266 265Figure 11-14 P01/SDA1 (Port 1) and P60/SDA0 (Port 6) 270 269Figure 11-18 P41/TM1IO, P42/TM5IOA, and P43/TM5IOB/HI0 (Port 4) Figure 11-19 P44/TM5IC/HI1 (Port 4) 271 270Figure 11-20 P45/OSDXO and P46/OSDXI (Port 4) 278 11.3 I/O Port Control Registers289 12 ROM Correction294 13 I2C Bus Controller308 14 H CounterFigure 14-2 provides a schematic diagram of an example counter operation. 14.1 Description 14.2 Block Diagram 14.3 H Counter OperationFigure 14-1 H Counter Block Diagram 311 14.4 H Counter Control Registers312 H CounterThis field stores the HI0 clock source count. It becomes x3FF on over- flow. This field stores the HI1 clock source count. It becomes x3FF on over- flow. 313 Appendix ARegister Map314 313Table A-2 Register Map: x00FC00 to x00FDFF 20 315 314Table A-3 Register Map: x00FE00 to x00FFFF 20 317 Appendix BMN102HF75K Flash EEPROM VersionB.1 DescriptionMN102HF75K Flash EEPROM Version 318 B.2 BenefitsB.3 Using the PROM Writer ModeFigure B-2 PROM Writer Hardware Setup Figure B-3 Pin Configuration for Socket Adaptor 319 MN102HF75K Flash EEPROM VersionUsing the PROM Writer Mode 318 Table B-2 PROM Writer Hardware Hardware Part Device MN102HF75KBF MN102HF85KDP 320 B.4 Using the Onboard Serial Programming Mode329 B.5 Reprogramming FlowB.6 Programming Times330 MN102H75K/F75K/85K/F85K LSI User's Manual Description Record of Changes (Ver.1.0 to 1.1)331 Using This ManualUsing This ManualP17 MN10200 Series Linear Addressing High-Speed Version LSI User Manual P17 MN102H Series LSI User Manual P24 P27 P27 332 2 P30 1.6 Pin DescriptionsI/O ports Figure 1-9 MN102H75K Pin Configuration in Single-Chip Mode 1.6.1 MN102H85K Pin Description Figure 1-9 MN102H85K Pin Configuration in Single-Chip Mode P30 1.6 Pin Descriptions 1.6.1 MN102H75K Pin Description P31 1.6.2 MN102H75K P in Description Figure 1-10 MN102H75K Pin Configuration in Single-Chip Mode P32 Table 1-3 Pin Function(Continued) P33 Table 1-3 Pin Function(Continued) P33 Figure 1-11 Power Supply Wring P34 Figure 1-12 Power Supply Wring64-Pin SDIP Top View Block Pin Name P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P61 P70-P77 P80-P87 Block I/O ports MN102H75K/HF75K: total 66 pins MN102H85K/HF85K: total 50 pins Pin Name P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P61 P70-P77 P80-P87 I/O ports only in MN102H75K/HF75K Power Supply AV AV MN102H75K Power Supply AVDD A V MN102H75K MN102H85K 333 P33 P37 P72 3.1 CPU Modes P72 3.1 CPU Modes Semiconductor Company, Matsushita Electric Industrial Co., Ltd.Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.panasonic.co.jp/semicon/ 338 SALES OFFICESNORTH AMERICA LATIN AMERICA EUROPE ASIA
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