Contents
Main
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Declaration of Conformity
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1General Information
2Hardware Configuration
2.1RS-422 or RS-485 Signal Line Termination
Jumpers J6-J9
2.2Signal Connections
2.3Full-duplex/Half-duplex Operation
Right Card Edge Jumpers
2.3.1CTS0_SEL, CTS1_SEL (J10,17)
4DSCLP/SSCLP-200/300 User's Manual
2.3.2AUX0_SEL1,0, AUX1_SEL1,0 (J12,11,19,18)
2.3.3RCLK0_SEL, RCLK1_SEL (J13, 20)
2.3.4TGL0_SEL1,0, TGL1_SEL1,0 (J15,14,22,21)
2.3.5RXEN0_SEL, RXEN1_SEL (J16, 23)
2.4Clock Rate and Optional Registers
2.4.1Enable Scratchpad Register (SPAD, J2)
2.4.2Force High-Speed UART Clock (X2 or X4, J4-J5)
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3Hardware Installation
4Address Map and Special Registers
4.1Base Address and Interrupt Level (IRQ)
4.2Enabling the Special Registers
4.3Interrupt Status Register
4.4Quatech Modem Control Register
4.5Options Register
4.5.1Enhanced Serial Adapter Identification
4.5.2Clock Rate Multiplier
5Windows Configurations
5.1Windows Millennium
5.2Windows 2000
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5.4Windows 95 5.5Using the "New Hardware Found" Wizard
5.6Viewing Resources with Device Manager
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6Other Operating Systems
6.1Windows NT
6.2OS/2
6.3DOS and other operating systems
6.3.1QTPCI.EXE
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7 External Connections
7.1RTS/CTS Handshake
7.2RCLK
7.3XCLK
7.4AUXIN/AUXOUT Loopback
7.5Half-Duplex/Full-Duplex Selection
Jumpers J6, J8
Figure 23 --- Half- or full-duplex selection
Figure 24 --- Output control block diagram DSCLP-200/300 User's Manual 29
7.6Termination Resistors
30 DSCLP/SSCLP-200/300 User's Manual
Jumpers J1-J4
Figure 25 --- RS-422/485 Line termination resistance values
7.7RS-422/485 Peripheral Connection
8PCI Resource Map
9Specifications
10 Troubleshooting