DIGITAL INPUT/OUTPUT CARD IOD-144 USER MANUAL
6-13
SHARING INTERRUPTS ON THE ISA BUS
As noted on pages 2-1 and 3-1, IOD-144 can accept external interrupts via bit C3 at each
24-bit group. On occasion, however, a system application will require more interrupt
levels than are available on the ISA bus. While not recommended, IRQ sharing is
possible. Each card that is going to share an IRQ must strictly adhere to a special
standard for accessing the IRQ line as follows:
a. The interrupt must be held in a high impedance state until asserting an
interrupt.
b. The interrupt must be asserted in the form of a low signal lasting at least 500
nanoseconds followed by a rising edge and then immediately returning to a
high impedance condition.
c. The card must contain a status register or flag of some kind to indicate that it
generated the interrupt. There is an exception to this rule. This is the case
where only one card of those sharing the interrupt level does not provide a
status bit to indicate that it asserted the interrupt but is otherwise capable of
sharing the IRQ. In this case, it may share the interrupt level with other cards
if (a) it is the only card on that IRQ level that does not have a status bit, and
(b) it is installed onto the IRQ vector first. (This makes it the last card to be
called in the vector chain.) This scheme will work because it can be assumed
that, if every other card in the vector chain did not cause the interrupt, then the
last card must be the one that did.
Note that, if two cards assert the IRQ line within 500 nanoseconds of each other, the
second card in the ISR chain will not be serviced. It's possible to alleviate this problem
by writing a single ISR that can detect the bit flag on every card and, therefore, detect the
fact that two (or more) cards report generating an interrupt even though only one interrupt
was processed by the CPU.