Access PCI-COM422/4 user manual Reception

The C command to set the UART for an 8-bit word, no parity, and one stop bit is:

outportb(BASEADDR +3, 0x03)

The final initialization step is to flush the receiver buffers. You do this with two reads from the receiver buffer at Base Address +0. When done, the UART is ready to use.

Reception

Reception can be handled in two ways: polling and interrupt-driven. When polling, reception is accomplished by constantly reading the Line Status Register at Base Address +5. Bit 0 of this register is set high whenever data are ready to be read from the chip. A simple polling loop must continuously check this bit and read in data as it becomes available. The following code fragment implements a polling loop and uses a value of 13, (ASCII Carriage Return) as an end-of-transmission marker:

do

{

while (!(inportb(BASEADDR +5) & 1)); /*Wait until data ready*/ data[i++]= inportb(BASEADDR);

}

while (data[i]!=13); /*Reads the line until null character rec'd*/

Interrupt-driven communications should be used whenever possible and is required for high data rates. Writing an interrupt-driven receiver is not much more complex than writing a polled receiver but care should be taken when installing or removing your interrupt handler to avoid writing the wrong interrupt, disabling the wrong interrupt, or turning interrupts off for too long a period.

The handler would first read the Interrupt Identification Register at Base Address +2. If the interrupt is for Received Data Available, the handler then reads the data. If no interrupt is pending, control exits the routine. A sample handler, written in C, is as follows:

readback = inportb(BASEADDR +2);

if (readback & 4) /*Readback will be set to 4 if data are available*/ data[i++]=inportb(BASEADDR);

outportb(0x20,0x20); /*Write EOI to 8259 Interrupt Controller*/ return;

Manual MPCICOM422-4.E1b Page 5-3