Acer 3300S manual Power-On Self-Test Post, Checkpoint Description

Power-On Self-Test (POST)

Each time you turn on the system, the Power-on Self Test (POST) is initiated. Several items are tested during POST, but is for the most part transparent to the user.

The Power-On Self Test (POST) is a BIOS procedure that boots the system, initializes and diagnoses the system components, and controls the operation of the power-on password option. If POST discovers errors in system operations at power-on, it displays error messages on screen, generates a check point code at port 80h or even halts the system if the error is fatal.

The main components on the main board that must be diagnosed and/or initialized by POST to ensure system functionality are as follows:

Microprocessor with built-in numeric co-processor and cache memory subsystem Direct Memory Access (DMA) controller (8237 module)

Interrupt system (8259 module) or APIC (advance program interrupt controller) Three programmable timers (system timer and 8254 module)

ROM subsystem RAM subsystem

CMOS RAM subsystem and real time clock/calendar with battery backup Onboard serial interface controller

Onboard parallel interface controller

Embedded hard disk interface and one diskette drive interface Keyboard and auxiliary device controllers

I/O ports

Two RS232 serial ports One parallel port

One PS/2-compatible mouse port

OnePS/2-compatible keyboard port

NOTE: When Post executes a task, it uses a series of preset numbers called check points to be latched at

port 80h, indicating the stages it is currently running. This latch can be read and shown on a debug board.

The following table describes the BIOS common tasks carried out by POST. Each task is denoted by an unique check point number. For other unique check point numbers that are not listed in the table, refer to the correspoing product service guide.

Post Checkpoints List: The list may vary accordingly depending on your BIOS.

Checkpoint	Description
CFh	Test CMOS R/W functionality
C0h	Early chipset initialization:
	-Disable shadow RAM
	-Disable L2 cache (socket 7 or below)
	-Program basic chipset registers
C1h	Detect memory
	-Auto-detection of DRAM size, type and ECC.
	-Auto-detection of L2 cache (socket 7 or below)
C3h	Expand compressed BIOS code to DRAM
C5h	Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.
0h1	Expand the Xgroup codes locating in physical address 1000:0
02h	Reserved

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