SPE C N O.
MT 220 WW 01 V. 0
PAG E
9/23
ALL RIGH TS RESE RVED ANY PORTION O F THIS DOCUMENT SHALL NOT BE REPRODUC ED, COP IED, O R TRANSF ORMED
TO ANY OTHER FORMS W ITHOUT
PRIOR
WRITTEN
PERMISS ION FROM INNOLUX DISPLAY CORP ORATION.

Note 4 : test condition :

(1) V
DD
= 5 V, V
DD
rising time = 470 s ± 10%
(2) Pattern: Mosaic pattern

(3) Test circuit

Note 5 : LVDS signal definition

VIN
+
= Positive differential DATA & CLK Input
VIN- = Negative differential DATA & CLK Input
VID = VIN
+
– VIN- ,
∆VCM =VCM
+
–VCM-,
∆VID =VID
+
–VID-,
VID+ =VIH
+
–VIH-,
VID- =VIL
+
–VIL-,
VCM = (VIN
+
+VIN-)/2,
VCM+ = (VIH
+
+VIH-)/2,
VCM- = (VIL
+
+VIL-)/2,
90
%
Ton=470 s 10%

V

DD
M2
M1
1K
C3
47K
R1
C1
5 V
12V
VDD ( LCD INPUT)
CONTROL SIGNAL
(HIGH to LOW)
2SK1399
2SK1059
R2
C2
10000pF
1uF
R3
47K
FUSE
1uF