Anritsu MP1763C 1-3

1-3

1.2 Specifications

CLOCK1/CLOCK1, CLOCK2 3 systems

Error

insertion

Error ratio 1 10 (n = 4 , 5, 6, 7 , 8 , 9)

Insertion

position

Insertion possible at any one of 32 channels

(Rear panel swith)

Error insertion by rising edge of external signal input

Insertion

position

Insertion possible at any one of 32 channels

(Rear panel switch)

DISABLE

function

Error insertion when external signal input level is “H”

1 10

Insertion

position

Insertion possible at any one of 32 channels

(Rear panel switch)

DATA is set to “0” while external signal input level is “L”.

External

Clock Input

0.05 12.5 GHz

0.4 to 2.5 Vp-p

0.05 to 0.5 GHz : Square wave only

> 0.5 GHz: Sine wave or square wave (duty 50 %)

50 Ω

Internal

External Eror

injection

Error ratio

Gating input

Frequency range

Input level

Input waveform

Input impedance

Connector SMA

Clock output Number of

outputs

Pattern

generation

-n

-n (n = 4 , 5, 6, 7 , 8 , 9)

CLOCK1

/ CLOCK1

CLOCK2

500 ps/1 ps step

Amplitude 0.25 to 2.0 Vp-p/Step 2 mV

Setting error: 15% (1.5 to 2.0 Vp-p), % (0.5 to 1.5 Vp-p),

Offset -2.0 to 2.0 V (V ) /Step 1 mV

Setting error: 15 % or 15 % of Amplitude, and 100 mV,

Rise/fall times

(10%–90%)

8 GHz 1.5 to 2 Vp-p 35 ps or less

8 GHz 1.5 to 2 Vp-p 50 ps or less

8 GHz 1.0 to 1.5 Vp-p 40 ps or less

8 GHz 1.0 to 1.5 Vp-p 55 ps or less

8 GHz 0.25 to 1.0 Vp-p 45 ps or less

8 GHz 0.25 to 1.0 Vp-p 60 ps or less

15 % or less or 150 mV, whichever is larger

Duty ratio adjust

function

Duty ratio can be adjusted by semifixed variable resistor

50 Ω (with back termination)

APC-3.5

V :

Amplitude: 1 Vp-p 35 %

50 Ω (without back termination)

SMA

Waveform distortion

Load impedance

Connector

Delay range

Connector

Load impedance

Output level

OH

OH

or single

or single

mV(0.25 to 0.5 Vp-p)

0 200 mV

whichever is larger

50 Ω/GND, 50 Ω/–2 VTermination

Contents

Main ii Safety Symbols Symbols used in manual Safety Symbols Used on Equipment and in Manual DANGER WARNING CAUTION iii iv v vi vii Equipment Certificate Anritsu Warranty Anritsu Corporation Contact viii Notes On Export Management Lifetime of Parts FOR CALIFORNIA USA ONLY Page x CE Conformity Marking CE marking 1. Product Model 2. Applied Directive 3. Applied Standards C-tick Conformity Marking xii Power Line Fuse Protection I Composition of MP1763C Operation Manuals II Title of Contents SECTION 3 DESCRIPTION OF PANELS AND CONNECTORS ............................. 3-1 SECTION 4 OPERATING INSTRUCTIONS ............................................................... 4-1 Page Page Page 1-2 1.2 Specifications 1-3 whichever is larger 1-4 1-5 1-6 Section 1 GENERAL 1-7 * When OPTION 03 is installed, there is no 1/8 output. 1-8 1.3 Composition 2-1 SECTION 2 PREPARATIONS 2.1 Environmental Conditions of Installation Site 2.2 Safety Measures 2-2 2.3 Power Connection 2.3.1 Power Requirements 2.3.2 Connecting the Power Cord 2-3 2.4 Damage Prevention Measures Page Page Section 3 DESCRIPTION OF PANELS AND CONNECTORS PULSE PATTERN GENERATOR MP1763C 0.05 - 12.5GHz INTERNAL CLOCK (OPTION.01) PATTERN MEMORY 3.1 FRONT PANEL 3-2 3-3 3-4 3.2 REAR PANEL Section 3 DESCRIPTION OF PANELS AND CONNECTORS !! Nameplate 3-5 Page Page 4-2 4-3 4.2 Generation Pattern Setting 4-4 4.2.1 Logic modification 4.2.2 Alternate pattern setting 4-5 4-6 4.2.3 DATA pattern setting 4-7 4.2.4 ZERO SUBSTITUTION 4-8 4.2.5 Pseudo random pattern setting 4-9 4.2.6 ERROR addition 4-10 4.2.7 Tracking 4-11 4.2.8 Pattern SYNC. position 4-12 4-13 4.3 Output Interface 4-14 4.3.1 DUMMY terminal voltage switching 4-15 4.3.2 Amplitude, offset, and delay setting 4-16 The output waveform is as follows for any of the above three settings: OFFSEET 2 V If VOH is changed to VTH: OFFSEET 1.5 V 4-17 4.3.3 Duty adjustment 4.3.4 Cross point adjustment 4-18 4.3.5 Offset voltage setting range Page Page Page Page 4-23 4.4.1 File save 4-24 4.4.2 File recall 4.4.3 Disk formatting 4-25 4.4.4 File deletion 4.4.5 Error messages 4-26 4.4.6 Floppy disk 4.4.7 Floppy disk precautions 4-27 4.5 Parameters initialization 4-28 4.6 Functions of the FUNCTION Switch 5-1 SECTION 5 PRINCIPLES OF OPERATION 5.1 Pseudorandom Pattern (PRBS Pattern) 5-2 1 2 3 4 5 6 5-3 5.2 Pattern Synchronized Output Period 5.2.1 Pseudorandom pattern 5.2.2 Programmable pattern 5-4 5.3 Bit shift for Alternate A/B select timing 6-1 SECTION 6 PERFORMANCE TEST MEMORY MEMORY 6.1 Test Equipment 6.2 Error Measurement 6-2 Section 6 PERFORMANCE TEST MEMORY 6.3 Test Method Output DATA amplitude 0.5 Vp-p offset 0 Vp-p CLOCK amplitude 0.5 Vp-p offset 0.0 V Delay 0 ps 6-3 6.5 Check Items Check the 1/8 SPEED output with the connection shown at the below. !! Check all the outputs with the connections DATA1 DATA2 - - - DATA8. Fig. 6.3-2 Connection of rear panel Page 7-1 SECTION 7 MAINTENANCE 7.1 Daily Maintenance 7.2 Storage Precautions 7.3 Transportation Page 8-1 SECTION 8 TROUBLESHOOTING AND REPAIR 8.1 Before Considering Trouble Page A-1 APPENDIX A PERFORMANCE TEST REPORT SHEET Page INDEX-1 INDEX