Anritsu MP1763C 4-6, 4.2.3 DATA pattern setting

4-6

Section 4 OPERATING INSTRUCTIONS

4.2.3 DATA pattern setting

Select DATA with the keys.

Set DATA LENGTH with the and keys.

Select the digit to be set with the keys.

Set DATA LENGTH with the keys.

DATA LENGTH setting steps

2 to 65526: STEP 1 bit

65536 to 131012: STEP 2 bits

See section 1.2, “Functions,” for the following.

Set the page that is displayed at the BIT display with the set

DATA LENGTH as 16 bits/page. BIT of the displayed page

can be changed.

Setting value: 1 to DATA LENGTH/16

(LENGTH is multiple of 16)

1 to INT (DATA LENGTH/16)+1

(LENGTH is not multiple of 16)

Change the BIT value with the button below the LED. When

LOGIC is positive, lighting of the LED indicates high level.

Used the PRESET ALL or PAGE key when changing DATA

collectively.

PAGE 0 or 1

All BITs of the displayed PAGE are set to 0 or 1.

ALL 0 or 1 Pressing this key holding down the GUARD

key sets all BITs specified by DATA

LENGTH to 0 or 1.

An optional pattern can be output repetitively.

When a 16-bit patern is set:

Pattern: 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0

1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1

DISPLAY

DATA LENGTH/ZERO SUBST LENGTH

DATA LENGTH

ZERO SUBST LENGTH

A / B LOOP TIME

PAGE/ PATTERN SYNC POSITION

DISPLAY

DATA LENGTH/ZERO SUBST LENGTH

DATA LENGTH

ZERO SUBST LENGTH

A / B LOOP TIME

PAGE/ PATTERN SYNC POSITION

Contents

Main ii Safety Symbols Symbols used in manual Safety Symbols Used on Equipment and in Manual DANGER WARNING CAUTION iii iv v vi vii Equipment Certificate Anritsu Warranty Anritsu Corporation Contact viii Notes On Export Management Lifetime of Parts FOR CALIFORNIA USA ONLY Page x CE Conformity Marking CE marking 1. Product Model 2. Applied Directive 3. Applied Standards C-tick Conformity Marking xii Power Line Fuse Protection I Composition of MP1763C Operation Manuals II Title of Contents SECTION 3 DESCRIPTION OF PANELS AND CONNECTORS ............................. 3-1 SECTION 4 OPERATING INSTRUCTIONS ............................................................... 4-1 Page Page Page 1-2 1.2 Specifications 1-3 whichever is larger 1-4 1-5 1-6 Section 1 GENERAL 1-7 * When OPTION 03 is installed, there is no 1/8 output. 1-8 1.3 Composition 2-1 SECTION 2 PREPARATIONS 2.1 Environmental Conditions of Installation Site 2.2 Safety Measures 2-2 2.3 Power Connection 2.3.1 Power Requirements 2.3.2 Connecting the Power Cord 2-3 2.4 Damage Prevention Measures Page Page Section 3 DESCRIPTION OF PANELS AND CONNECTORS PULSE PATTERN GENERATOR MP1763C 0.05 - 12.5GHz INTERNAL CLOCK (OPTION.01) PATTERN MEMORY 3.1 FRONT PANEL 3-2 3-3 3-4 3.2 REAR PANEL Section 3 DESCRIPTION OF PANELS AND CONNECTORS !! Nameplate 3-5 Page Page 4-2 4-3 4.2 Generation Pattern Setting 4-4 4.2.1 Logic modification 4.2.2 Alternate pattern setting 4-5 4-6 4.2.3 DATA pattern setting 4-7 4.2.4 ZERO SUBSTITUTION 4-8 4.2.5 Pseudo random pattern setting 4-9 4.2.6 ERROR addition 4-10 4.2.7 Tracking 4-11 4.2.8 Pattern SYNC. position 4-12 4-13 4.3 Output Interface 4-14 4.3.1 DUMMY terminal voltage switching 4-15 4.3.2 Amplitude, offset, and delay setting 4-16 The output waveform is as follows for any of the above three settings: OFFSEET 2 V If VOH is changed to VTH: OFFSEET 1.5 V 4-17 4.3.3 Duty adjustment 4.3.4 Cross point adjustment 4-18 4.3.5 Offset voltage setting range Page Page Page Page 4-23 4.4.1 File save 4-24 4.4.2 File recall 4.4.3 Disk formatting 4-25 4.4.4 File deletion 4.4.5 Error messages 4-26 4.4.6 Floppy disk 4.4.7 Floppy disk precautions 4-27 4.5 Parameters initialization 4-28 4.6 Functions of the FUNCTION Switch 5-1 SECTION 5 PRINCIPLES OF OPERATION 5.1 Pseudorandom Pattern (PRBS Pattern) 5-2 1 2 3 4 5 6 5-3 5.2 Pattern Synchronized Output Period 5.2.1 Pseudorandom pattern 5.2.2 Programmable pattern 5-4 5.3 Bit shift for Alternate A/B select timing 6-1 SECTION 6 PERFORMANCE TEST MEMORY MEMORY 6.1 Test Equipment 6.2 Error Measurement 6-2 Section 6 PERFORMANCE TEST MEMORY 6.3 Test Method Output DATA amplitude 0.5 Vp-p offset 0 Vp-p CLOCK amplitude 0.5 Vp-p offset 0.0 V Delay 0 ps 6-3 6.5 Check Items Check the 1/8 SPEED output with the connection shown at the below. !! Check all the outputs with the connections DATA1 DATA2 - - - DATA8. Fig. 6.3-2 Connection of rear panel Page 7-1 SECTION 7 MAINTENANCE 7.1 Daily Maintenance 7.2 Storage Precautions 7.3 Transportation Page 8-1 SECTION 8 TROUBLESHOOTING AND REPAIR 8.1 Before Considering Trouble Page A-1 APPENDIX A PERFORMANCE TEST REPORT SHEET Page INDEX-1 INDEX