4.4.2CPU Configuration

The items in this menu show the CPU-related information that the BIOS automatically detects.

BIOS SETUP UTILITY

Advanced

CPU Configuration

Module Version: 14.08

Physical Count: 1

Logical Count: 1

AMD Athlon(tm) 64 Processor 3200+ Revision: D0

Cache L1: 128KB

Cache L2: 512KB

Speed: 2000 MHz

Current FSB Multiplier: 10x

Maximum FSB Multiplier: 10x

Able to Change Freq: Yes

uCode Patch Level: 0x4D

GART Error Reporting

[Disabled]

MTRR

Mapping

[Continuous]

Cool

`n’ Quiet

[Disabled]

HT Link Speed

[Auto]

Memory Configuration

This option should remain disabled for the normal operation. The driver developer may enable it for testing purpose.

Select Screen

Select Item

+- Change Option

F1 General Help

F10 Save and Exit

ESC Exit

v02.58 (C)Copyright 1985-2005, American Megatrends, Inc.

GART Error Reporting [Disabled]

Allows you to enable or disable GART error checking for testing purposes. Configuration options: [Disabled] [Enabled]

MTRR Mapping [Continuous]

Determines the method used for programming processor MTRRs when using more than 4 GB of system memory. Setting to [Discrete] leaves the PCI hole below the 4 GB boundary undescribed. [Continuous] explicitly describes the PCI hole as non-cacheable. Configuration options: [Continuous] [Discrete]

Cool ‘n’ Quiet [Disabled]

Enables or disables the Cool ‘n’ Quiet™ technology feature. Configuration options: [Enabled] [Disabled]

HT Link Speed [Auto]

Allows you to set the speed at which the HyperTransport link will run if the speed is lower than or equal to the system clock and if the board is capable. Configuration options: [Auto] [200 MHz] [400 MHz] [600 MHz] [800 MHz] [1 GHz]

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Chapter 4: BIOS setup