4.4.2Chipset Configuration
The Chipset configuration menu allows you to change advanced chipset settings. Select an item then press <Enter> to display the
BIOS SETUP UTILITY
Advanced
Advanced Chipset Settings
WARNING: Setting wrong values in below sections may cause system to malfunction.
North Bridge Configuration
Intel
South Bridge Configuration
Configure North Bridge features.
←→ Select Screen
↑↓ Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit ESC Exit
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North Bridge Configuration
The North Bridge Configuration menu allows you to change the Northbridge settings.
BIOS SETUP UTILITY
Advanced
| NorthBridge Chipset Configuration | Sequencing: | |||
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| allocates address | |
| MCH Branch Mode | [Branch Interleave] | branch 0 then 1. | ||
| Interleaving: | ||||
| Patrol Scrubbing | [Enabled] | interleaves branch | ||
| Demand Scrubbing | [Disabled] | across branches. | ||
| Branch Dependent Sparing | [Disabled] | Mirroring: | ||
| Branch 0 | [Enabled] | mirrors branch | ||
| Branch Specific Sparing | [Disabled] | space |
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| Rank Interleaving | [4:1] |
| between branches. | |
| Branch 1 | [Enabled] | Single Channel: | ||
| Branch Specific Sparing | [Disabled] | forces single | ||
| Rank Interleaving | [4:1] |
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| MemCool Mode | [Disabled] |
| Select Screen | |
| Intel QuickData Tech. | [Enabled] | ←→ | ||
| ↑↓ | Select Item | |||
| PCIe Link Speed | [Auto] | +- | Change Option | |
| PCIE1 Slot Payload Size | [Auto] | F1 | General Help | |
| PCIE3 Slot Payload Size | [Auto] | F10 | Save and Exit | |
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| ESC | Exit |
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MCH Branch Mode [Branch Interleave]
Allows you to select the MCH branch mode.
Configuration options: [Branch Sequencing] [Branch Interleave] [Branch Mirroring] [Single Channel 0]
Patrol Scrubbing [Enabled]
Enables or disables the Patrol Scrubbing.
Configuration options: [Disabled] [Enabled]
Chapter 4: BIOS setup |