Secondary Timings
DRAM RAS# to RAS# Delay [Auto] Configuration options: [Auto] [1] – [15]
DRAM REF Cycle Time [Auto] Configuration options: [Auto] [1] – [511]
DRAM Refresh Interval [Auto] Configuration options: [Auto] [1] – [65535]
DRAM WRITE Recovery Time [Auto]
Configuration options: [Auto] [1] – [16]
DRAM READ to PRE Time [Auto]
Configuration options: [Auto] [1] – [15]
DRAM FOUR ACT WIN Time [Auto]
Configuration options: [Auto] [1] – [255]
DRAM WRITE to READ Delay [Auto]
Configuration options: [Auto] [1] – [15]
DRAM CKE Minimum pulse width [Auto]
Configuration options: [Auto] [1] – [15]
DRAM CAS# Write Latency [Auto]
Configuration options: [Auto] [1] – [31]
RTL IOL control
DRAM RTL Initial Value [Auto] Configuration options: [Auto] [1] - [63]
DRAM RTL (CHA_R0D0) [Auto] Configuration options: [Auto] [1] - [63]
DRAM RTL (CHA_R0D1) [Auto] Configuration options: [Auto] [1] - [63]
DRAM RTL (CHA_R1D0) [Auto] Configuration options: [Auto] [1] - [63]
DRAM RTL (CHA_R1D1) [Auto] Configuration options: [Auto] [1] - [63]
DRAM RTL (CHB_R0D0) [Auto] Configuration options: [Auto] [1] - [63]
DRAM RTL (CHB_R0D1) [Auto] Configuration options: [Auto] [1] - [63]
DRAM RTL (CHB_R1D0) [Auto] Configuration options: [Auto] [1] - [63]
Chapter 3
ASUS MAXIMUS VI GENE |