Asus P5LD2-VP, P5LD2-FM, P5LD2-DH Chipset, Configure Dram Timing by SPD Enabled, Clocks 6 Clocks

2.4.4 Chipset

The Chipset menu allows you to change the advanced chipset settings. Select an item then press <Enter> to display the sub-menu.

Advanced Chipset Settings
Configure DRAM Timing by	SPD	[Enabled]
Booting Graphic Adapter	Priori	[PCI Express/PCI]

Configure DRAM Timing by SPD [Enabled]

When this item is enabled, the DRAM timing parameters are set according to the DRAM SPD (Serial Presence Detect). When disabled, you can manually set the DRAM timing parameters through the DRAM sub-items. The following sub-items appear when this item is Disabled. Configuration options: [Disabled] [Enabled]

DRAM CAS# Latency [5 Clocks]

Controls the latency between the SDRAM read command and the time the data actually becomes available.

Configuration options: [6 Clocks] [5 Clocks] [4 Clocks] [3 Clocks]

DRAM RAS# Precharge [4 Clocks]

Controls the idle clocks after issuing a precharge command to the DDR SDRAM. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks]

[5 Clocks] [6 Clocks]

DRAM RAS# to CAS# Delay [4 Clocks]

Controls the latency between the DDR SDRAM active command and the read/write command. Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] [6 Clocks]

DRAM RAS# Activate to Precharge [15 Clocks] Sets the RAS Activate timing to Precharge timing. Configuration options: [4 Clock] [5 Clocks] ~ [18 Clocks]

DRAM Write Recovery Time [4 Clocks]

Sets the DRAM Write Recover Time.

Configuration options: [2 Clocks] [3 Clocks] [4 Clocks] [5 Clocks] [6 Clocks]

ASUS P5LD2-FM/DH/VP 2-19