XRD9829REF
Control Registers
Function | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
(Register |
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| State |
S1/S0) |
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| (Note 1) |
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Gain |
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(00) | G5 | G4 | G3 | G2 | G1 | G0 | X | X | 000000XX |
(MSB) |
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| (LSB) |
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Offset | O7 | O6 | O5 | O4 | O3 | O2 | O1 | O0 | 01000000 |
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(01) | (MSB) |
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| (LSB) |
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Mode | X | X | VRT | INPUTDC | DC/AC | CIS/CCD | MUX SEL | MUX SEL | XX000000 |
(10) |
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| 0: INTERNAL | REFERENCE | 0: DC | 0: CIS |
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| 1: EXTERNAL | (VDCREF) | 1: AC | 1: CCD |
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| 0:INTERNAL |
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| 0 0: VIN0 | 0 0: VIN0 |
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| (VDCREF= |
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| 0 1: VIN1 | 0 1: VIN1 |
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| AGND) |
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| 1 0: VIN2 | 1 0: VIN2 |
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| 1: EXTERNAL |
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| 1 1: VIN3 | 1 1: VIN3 |
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| (VDCREF=VDCEXT) |
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Mode |
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& Test |
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(11) | X | X | X | DIGITAL RESET | TEST3 | TEST2 | TEST1 | X | XXX0000X |
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| 0: NO RESET | 0: TEST3 | 0: TEST2 | 0: TEST1 |
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| 1: RESET | DISABLED | DISABLED | DISABLED |
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| (REGISTERS ARE | 1: OUTPUT | 1: OUTPUT | 1: VIN1 PIN |
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| RESETTO | OFBUFFER | OF PGA | TIED TO |
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| TIED TO VIN3 | TIED TO | INPUT OF |
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| STATES) | PIN (VIN3 PIN | VIN2 PIN | ADC |
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| BECOMES | (VIN2 PIN | (PGA OUTPUT |
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| ANOUTPUT) | BECOMES | DISCONNECTED |
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| ANOUTPUT) | FROMINPUT |
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| OFADC) |
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Table 1. Control Register Description for XRD9829
Note:
1These are the control register settings upon initial
Rev. 1.00
7