Clevo 2700C Features, Host Interface Controller, Integrated DRAM Controller

Service Manual

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The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the Ultra DMA33/66/100 function that supports the data transfer rate up to 100 MB/s. It provides the separate data path for two IDE channels that can eminently improve the performance under the multi-tasking environ- ment.

The following illustrates the system block diagram

FeaturesHost Interface Controller

–Supports Intel Slot 1/Socket370 Pentium II/!!! CPUs

–Synchronous Host/DRAM Clock Scheme

–Asynchronous Host/DRAM Clock Scheme

Integrated DRAM Controller

–3-DIMM/6-Bank of 3.3V SDRAM

–Supports Memory Bus up to 133 MHz

–System Memory Size up to 3 GB

–Up to 512MB per Row

–Supports 16Mb, 64Mb, 128Mb, 256Mb, 512Mb SDRAM Technology

–Suspend-to-RAM (STR)

–Relocatable System Management Memory Region

–Programmable Buffer Strength for CS#, DQM[7:0], WE#, RAS#, CAS#, CKE, MA[14:0] and MD[63:0]

–Shadow RAM Size from 640KB to 1MB in 16KB increments

–Two Programmable PCI Hole Areas

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