Clevo 2700C 81

Service Manual

C69

5P

REF_IN

Y3

P0AC

P1CL

P2LI

P3TD

P4RD

C70

5P

25M

REF_OUT

VDD3

PVCC3

(10)

CRS

CRS

R65

22

Z12

COL

R66

22

Z13

(10)

COL

T XD3

8

RN5

1

Z14

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

U7

(10)

T XD3

T XD2

7

2

Z15

COL CRS IOVDD

_OUTREF

INREF IOVDD

0ACP

IOVSS DVSS

RVSS

P1CL P2LI

TVSS 3TDP

TVDD

4RDP

(10)

T XD2

T XD1

6

8P4R_22

3

Z16

VDD3

(10)

T XD1

PVCC3

(10)

T XD0

T XD0

5

4

Z17

(10)

TXEN

TXEN

R74

22

48

T XD3

NOD/REP

1

NOD/REP

47

T XD2

10/100SEL

2

TXCLK

R86

22

46

3

TP_CP

(10)

TXCLK

45

T XD1

TP_CP

4

Z18

44

T XD0

VSS_T

5

LTX+

Z19

43

TXEN

TP_TX+

6

LTX-

R84

TXER

42

TXCLK

TP_TX-

7

TXER

VDD_T

1K

41

RXTRI

VDD_R

8

40

VSS_IO

10TCSR

9

10TCSR

Z20

39

10

100TCSR

Z21

38

RXER

100TCSR

11

37

RXCLK

VSS_R

12

RXER

R85

22

Z22

36

VDD_IO

VSS_R

13

LRX+

(10)

RXER

35

RXDV

TP_RX+

14

LRX-

RXCLK

R101

22

34

RXD0

TP_RX-

15

(10)

RXCLK

33

RXD1

VDD_R

16

RXDV

RXD2

VDD_R

R100

22

(10)

RXDV

RESETN

RXD3 MDC MDIO

VSS_IO

VSS_D LOCK

ANSEL

VDD D DPXSEL

HW/SW

VSS_R LSTA

NC

MII/SI

VSS_R

RN9

ICS1893

(10)

RXD0

RXD0

4

5

Z23

32

31 30

29

28

27

26

25

24

23

22

21

20

19

18

17

RXD1

3

6

Z24

(10)

RXD1

RXD2

2

7

Z25

(10)

RXD2

RXD3

1

8

Z26

(10)

RXD3

VDD3

8P4R_22

VDD3

HW/SW

II/SIM

RESET -

R94

10K

R98

1.5K

C104

VDD3

.1U

MDC

R99

22

Z27

(10)

MDC

MDIO

R97

22

Z28

(10)

MDIO

LRX+

LRX+

R52

C55

NEAR TO 1893

61.9(1%)

C

Z663

VDD3

C54

1.HW/SW=1

.1U

R53

C53

C

HW/SW

R96

1K

61.9(1%)

TP43

SW MODE

LRX-

LRX-

2.MII/SI=0

MII/SI

R95

1K

LTX+

LTX+

MII MODE

LTX-

3.NOD/REP=0

NOD/REP

R62

1K

LTX-

NODE OPERATION

R60

R61

TP44

10/100SEL: 10/100MHZ INDECATED

TP_CP

61.9(1%)

61.9(1%)

LOW=10 BASE-T ,

Z664

C52

HIGH=100BASE-T

DPXSEL: HALF OR FULL INDECATED

C66

C

LOW=HALF-DUPLEX,

.1U

HIGH=FULL-DUPLEX

ANSEL: AUTO-NEGOTITATION INDECATED

LOW=DISABLE,

HIGH=ENABLE

VDD3

	PVCC3				1	L17
PVCC3	PVCC3				1	2
PVCC3
	C103	C102	C82	C83	C67	BEAD(1206)
	C103	C102	C82	C83	C67
	.1U	.1U	.1U	.1U	.1U

VDD3

C68 C106 C105 C71

.1U

.1U

.1U

.1U

SET TRANSMIT TING DRIVING CURRENT			SET PHY
SET TRANSMIT TING DRIVING CURRENT			ADDRESS=00001
					VDD3
10TCSR	R118	2K(1%)	P0AC	R67	1K
10TCSR			(ADD0)
			P1CL	R64	1K
	C122	C	(ADD1)
	C122	C
R82	12.1K		P2LI	R55	1K
VDD3			(ADD2)
VDD3
	R83	1.54K(1%)	P3TD	R63	1K
100TCSR			(ADD3)
			P4RD	R54	1K
	C94	C	(ADD4)
	C94	C

CN2

1

U20

16

RD+

1

RX+

RD+

2

14

Z78

2

RX-

RDC

Z263

3

15

RD-

RXC

RD-

3

Z264

4

NC

NC

13

Z518

TP22

R18

0(R)

4

7

10

TD+

R19

0(R)

5

TX+

TD+

6

11

Z79

T XC

T DC

6

8

9

T D-

TX-

TD-

Z656

Z262

Z517

5

12

Z579

7

9

NC

NC

TP23

8

10

H0009

R8

R9

R41

R40

LAN RJ-458P

75

75

75

75

RING

RING

(15)

TIP

Z80

TIP

(15)

L7

BEAD(1206)

C21

1000P(1210)2KV

Title

LAN PHY

Size

Document Number

Rev

Custom

0200-13.SCH

71-22C00-D02

A

Date:

Monday, March05, 2001

Sheet

14

of

31

B - 14

Contents

Page Notice Chapter 1: Introduction Chapter 2: Chipset and Mainboard information Chapter 3: Disassembly Appendix A: Mechanical Drawings and Parts Lists Appendix B: Schematic Diagrams Appendix C: Switch Settings Chapter 1: Introduction System specifications (general) CPU ( FC-PGA370) Memory TouchPad Keyboard HDD BIOS Display LCD\TFT Audio Power Supply Physical Page CPU Page Chipsets Features Host Interface Controller Integrated DRAM Controller Integrated A.G.P. Compliant Target/66Mhz Host-to-PCIBridge Meet PC99 Requirements PCI 2.2 Specification Compliant High Performance PCI Arbiter Integrated Host-To-PCIBridge Virtual PCI-to-PCIBridge Integrated Ultra AGP VGA for Hardware 2D/3D Video/Graphics Accelerators Page Low Pin Count Interface Advanced PCI H/W Audio & Modem Advanced Power Management Integrated DMA Controller Integrated Interrupt Controller Three 8254 Compatible Programmable 16-bitCounters Integrated Keyboard Controller Integrated Real Time Clock (RTC) with 256B CMOS SRAM Universal Serial Bus Host Controller I2C Bus/SMBUS Series Interface NAND Tree for Ball Connectivity Testing 672-BallsBGA Package 1.8V Core with Mixed 3.3V and 5V I/O CMOS Technology PC Card Chipset - PCI1410 Page Ports Mainboard Mainboard photo Page Chapter 3: Disassembly Size chart for screws and hex nuts: Letter Disassembly steps Steps to remove the HDD: Steps to remove the inverter board: Steps to remove the LCD panel: Steps to remove the mainboard: Removal Procedures Remove the keyboard Remove the HDD assembly Remove the CD-ROM\DVD-ROMassembly Remove the heat sink Applying a heat sink pad Remove the CPU Reinstall the CPU Separate the notebook base in two Page Page Remove the FDD assembly Remove the CD-ROMtray 1 2Remove the Fan Remove the mainboard and tray from the bottom case Remove the mainboard from the mainboard tray The LCD Panel Remove the LCD panel and bracket from the LCD panel case Page Remove the LCD panel from the bracket Page Page LCD panel (13.1” , 15.3”) assembly and parts list Page Keyboard and Touchpad assembly Page FDD assembly and parts list HDD assembly and parts list CD-ROMassembly and parts list Page Bottom half assembly and parts list 2700C Page Page Page Keyboard and Touchpad parts list FDD Assembly and parts list Page Page Page Page Appendix B: Schematic Diagrams Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Appendix C: Switch Settings Clock Settings (SW6) CPU (FSB) SDRAM SW6-1 Panel ID Settings (SW7) SIZE BRAND Model No SW7-1