CPBH Series | CyberResearch® CPU Cards |
4.6Advanced Chipset Features
This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and the access to the system memory resources, such as DRAM and the external cache. It also coordinates the communications between the conventional ISA and PCI buses. It must be stated that these items should never be altered. The default settings have been chosen because they provide the best operating conditions for your system. You might consider and make any changes only if you discover that the data has been lost while using your system.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable | By SPD |
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CAS Latency Time | 2 |
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| Menu Level | X |
Active to Precharge Delay | 8 |
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DRAM RAS# to CAS# Delay | 4 |
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DRAM RAS# Precharge | 4 |
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| Change the day, month, | |
Memory Frequency For | Auto |
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System BIOS Cacheable | Enabled |
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Video BIOS Cacheable | Enabled |
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Memory Hole At | Disabled |
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Delay Prior to Thermal | 16 Min |
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AGP Aperture Size (MB) | 128 |
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Init Display First | PCI Slot |
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** |
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Enabled |
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16MB |
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Boot Display | Auto |
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Panel Scaling | Auto |
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Panel Number | 1 |
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TV Standard | Off |
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Video Connector | Automatic |
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TV Format | Auto |
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ÇÈÆÅ: Select Item + / | F10: Save | ESC: Quit F1: General Help | |||
F5: Previous Values | F6: | F7: Optimized Defaults | |||
32 | ©Copyright 2005 CyberResearch, Inc |