CY7C185 Document #: 38-05043 Rev. *A Page 5 of 11
Switching Waveforms
10. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
11. WE is HIGH for read cycle.
12. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL.
13. The internal write time of the memory is defined by the overla p of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH
to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
14. During this period, the I/Os are in the output state and input signals shou ld not be applied.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No.1[10,11]
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE tHZCE
tPD
OE
HIGH
DATA OUT
VCC
SUPPLY
CURRENT
CE1
OE
CE2
Read Cycle No.2[12,13]
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATA INVALID
CE
CE1
OE
WE
CE2
DATA I/O
tSCEI
tSCE2
ADDRESS
NOTE 14
[11,13]