Cypress 7C185-15, 7C185-20, 7C185-25, 7C185-35 Switching Waveforms

CY7C185
Document #: 38-05043 Rev. *A Page 6 of 11
Notes:
15. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
tWC
tAW
tSA
tHA
tHD tSD
tSCE1
WE
DATA I/O
ADDRESS
CE1
DATA INVALID
tSCE2
CE2
rite Cycle No. 2 (CE Controlled)[13,14,15]
tHD tSD
tLZWE
tSA
tHA tAW
tWC
tHZWE
DATA INVALID
tSCE1
tSCE2
CE1
CE2
ADDRESS
DATA I/O
WE
Write Cycle No. 3 (WE Controlled, OE LOW)[13,14,15,16]
NOTE 14