Cypress CY24713 manual AC Electrical Characteristics VDD =, Μ F, CLK out

CY24713

AC Electrical Characteristics (VDD = 3.3V)

Parameter[3]	Description	Conditions	Min	Typ.	Max	Unit
DC	Output Duty Cycle	Duty Cycle is defined in Figure 3 50% of VDD	45	50	55	%
ER0	Rising Edge Rate	Output Clock Edge Rate, Measured from 20% to	0.8	1.4	–	V/ns
		80% of VDD, CLOAD = 15 pF Figure 4.
EF1	Falling Edge Rate	Output Clock Edge Rate, Measured from 80% to	0.8	1.4	–	V/ns
		20% of VDD, CLOAD = 15 pF Figure 4.
t9	Clock Jitter	Peak-Peak period jitter maximum absolute jitter	–	200	250	ps
t10	PLL Lock Time		–	–	3	ms

Figure 2. Test Circuit

VDD

0.1 μ F

OUTPUTS

CLK out

C LOAD

GND

Figure 3. Duty Cycle Definition; DC = t2/t1

CLK

t1
t2
50%	50%

Figure 4. Rise and Fall Time Definitions: ER = 0.6 x VDD/t3, EF = 0.6 x VDD/t4

CLK

t3	t4
	80%
	20%

Note

3. Not 100% tested

Document #: 38-07396 Rev. *A Page 3 of 5

[+] Feedback