Cypress CY62126EV30

MoBL®, CY62126EV30

Document #: 38-05486 Rev. *E Page 11 of 13

Figure 12. 44-Pin TSOP II (51-85087)

Package Diagrams (continued)

51-85087-*A

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Contents

Main MoBL,CY62126EV30 1-Mbit (64K x 16) Static RAM Features Functional Description Logic Block Diagram MoBL, CY62126EV30 Pin Configurations MoBL, CY62126EV30 Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance Data Retention Characteristics Switching Characteristics MoBL, CY62126EV30 Document #: 38-05486 Rev. *E Page 6 of 13 PREVIOUS DATA VALID DATA VALID Switching Waveforms Figure 5. Read Cycle No. 1(Address transition controlled)[15, 16] Switching Waveforms Document #: 38-05486 Rev. *E Page 8 of 13 Figure 9. Write Cycle No. 3 (WE controlled, OE LOW [19] Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[19] Truth Table Ordering Information Document #: 38-05486 Rev. *E Page 10 of 13 Package Diagrams Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150) 51-85150-*D Page MoBL, CY62126EV30 Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions