Cypress CY7C1018CV33 AC Test Loads and Waveforms4, Read Cycle, Write Cycle 9, Parameter, Unit

CY7C1018CV33

AC Test Loads and Waveforms[4]

R 317Ω

3.3V

OUTPUT

30 pF	R2
	351Ω

(a)

High-Z characteristics: R 317Ω

3.3V

OUTPUT

5 pF	R2
	351Ω

(c)

3.0V

GND

Rise Time: 1 V/ns

ALL INPUT PULSES

90%

10%

(b)

90%

10%

Fall Time: 1 V/ns

Switching Characteristics Over the Operating Range[5]

				-10			-12			-15
	Parameter		Description									Unit
				Min.	Max.	Min.		Max.	Min.		Max.
Read Cycle
tRC		Read Cycle Time		10		12			15			ns
tAA		Address to Data Valid			10			12			15	ns
tOHA		Data Hold from Address Change		3		3			3			ns
tACE			LOW to Data Valid		10			12			15	ns
		CE
tDOE			LOW to Data Valid		5			6			7	ns
		OE
tLZOE			LOW to Low-Z	0		0			0			ns
		OE
t			HIGH to High-Z[6, 7]		5			6			7	ns
	HZOE	OE
t			LOW to Low-Z[7]	3		3			3			ns
	LZCE	CE
tHZCE			HIGH to High-Z[6, 7]		5			6			7	ns
		CE
t	[8]		LOW to Power-up	0		0			0			ns
		CE
	PU
t	[8]		HIGH to Power-down		10			12			15	ns
		CE
	PD
Write Cycle[9, 10]
tWC		Write Cycle Time		10		12			15			ns
tSCE			LOW to Write End	8		9			10			ns
		CE
tAW		Address Set-up to Write End		8		9			10			ns
tHA		Address Hold from Write End		0		0			0			ns
tSA		Address Set-up to Write Start		0		0			0			ns
tPWE			Pulse Width	7		8			10			ns
		WE
tSD		Data Set-up to Write End		5		6			8			ns
tHD		Data Hold from Write End		0		0			0			ns
tLZWE			HIGH to Low-Z[7]	3		3			3			ns
		WE
tHZWE			LOW to High-Z[6, 7]		5			6			7	ns
		WE

Notes:

4.AC characteristics (except High-Z) for all speeds are tested using the Thèvenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c).

5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

6.tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.

7.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

8.This parameter is guaranteed by design and is not tested.

9.The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.

10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

Document #: 38-05131 Rev. *D Page 3 of 7

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