Cypress CY7C1018CV33 manual Features, Functional Description1, Logic Block Diagram, Top View

CY7C1018CV33

128K x 8 Static RAM

Features

•Pin- and function-compatible with CY7C1018BV33

•High speed

—tAA = 10 ns

•CMOS for optimum speed/power

•Center power/ground pinout

•Data retention at 2.0V

•Automatic power-down when deselected

•Easy memory expansion with CE and OE options

•Available in Pb-free and non Pb-free 300-mil-wide 32-pin SOJ

Functional Description[1]

device has an automatic power-down feature that significantly reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).

Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW).

The CY7C1018CV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This

The CY7C1018CV33 is available in a standard 300-mil-wide SOJ.

Logic Block Diagram
					I/O0
		INPUT BUFFER
A0					I/O1
A1	DECODER				I/O2
A2			128K x 8	AMPS
A43					I/O3
A				SENSE
A5	ROW		ARRAY
A6					I/O4
A7
A8					I/O5
			COLUMN	POWER	I/O6
CE				DOWN
			DECODER
					I/O7
WE
OE	9	10	11 12 13 14 15 16
	A A A A A A A A

Pin Configurations

		SOJ
	Top View
A0	1	32	A16
A1	2	31	A15
A2	3	30	A
A3			14
	4	29	A
CE	5	28	13
			OE
I/O0	6	27	I/O
		26	7
I/O1	7		I/O6
VCC	8	25	V
VSS		24	SS
	9		VCC
I/O2	10	23	I/O5
I/O3	11	22	I/O
			4
WE	12	21	A12
A4	13	20	A11
A5	14	19	A10
A6	15	18	A9
A7	16	17	A8

Note:

1.For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05131 Rev. *D		Revised August 3, 2006

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