
CY7C1018CV33
128K x 8 Static RAM
Features
•Pin- and
•High speed
—tAA = 10 ns
•CMOS for optimum speed/power
•Center power/ground pinout
•Data retention at 2.0V
•Automatic
•Easy memory expansion with CE and OE options
•Available in
Functional Description[1]
device has an automatic
Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
The CY7C1018CV33 is a
The CY7C1018CV33 is available in a standard
Logic Block Diagram |
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| I/O0 |
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| INPUT BUFFER |
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A0 |
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| I/O1 |
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A1 | DECODER |
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| I/O2 |
A2 |
| 128K x 8 | AMPS | ||
A43 |
| I/O3 | |||
A |
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| SENSE |
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A5 | ROW |
| ARRAY |
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A6 |
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| I/O4 |
A7 |
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A8 |
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| I/O5 |
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| COLUMN | POWER | I/O6 |
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CE |
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| DOWN |
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| DECODER |
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| I/O7 | |
WE |
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OE | 9 | 10 | 11 12 13 14 15 16 |
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A A A A A A A A |
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Pin Configurations
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| SOJ |
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| Top View |
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A0 | 1 | 32 | A16 |
A1 | 2 | 31 | A15 |
A2 | 3 | 30 | A |
A3 |
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| 14 |
4 | 29 | A | |
CE | 5 | 28 | 13 |
OE | |||
I/O0 | 6 | 27 | I/O |
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| 26 | 7 |
I/O1 | 7 | I/O6 | |
VCC | 8 | 25 | V |
VSS |
| 24 | SS |
9 | VCC | ||
I/O2 | 10 | 23 | I/O5 |
I/O3 | 11 | 22 | I/O |
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| 4 | |
WE | 12 | 21 | A12 |
A4 | 13 | 20 | A11 |
A5 | 14 | 19 | A10 |
A6 | 15 | 18 | A9 |
A7 | 16 | 17 | A8 |
Note:
1.For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation | • | 198 Champion Court • San Jose, CA | • | |
Document #: |
| Revised August 3, 2006 |
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