CY7C107B
CY7C1007B
AC Test Loads and Waveforms
5V | R1 480Ω | 5V | R1 480Ω | ||||||
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| 3.0V | ||
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ALL INPUT PULSES
OUTPUT |
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| OUTPUT |
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| 10% |
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30 pF |
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| R2 |
| 5 pF |
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| R2 | GND |
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INCLUDING |
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| 255Ω | INCLUDING |
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| 255Ω | ≤ 3 ns |
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JIG AND |
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| JIG AND |
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SCOPE | (a) |
| SCOPE | (b) |
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Equivalent to: |
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| THÉ VENIN EQUIVALENT |
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| OUTPUT |
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| 167Ω |
| 1.73V |
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90%
90%
10%
≤ 3 ns
Switching Characteristics[5] Over the Operating Range
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Parameter |
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| Description | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit |
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READ CYCLE |
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tRC |
| Read Cycle Time | 12 |
| 15 |
| 20 |
| 25 |
| 35 |
| ns | ||
tAA |
| Address to Data Valid |
| 12 |
| 15 |
| 20 |
| 25 |
| 35 | ns | ||
tOHA |
| Data Hold from Address | 3 |
| 3 |
| 3 |
| 3 |
| 3 |
| ns | ||
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| Change |
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tACE |
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| LOW to Data Valid |
| 12 |
| 15 |
| 20 |
| 25 |
| 35 | ns |
| CE |
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tLZCE |
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| LOW to Low Z[6] | 3 |
| 3 |
| 3 |
| 3 |
| 3 |
| ns |
| CE |
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tHZCE |
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| HIGH to High Z[6, 7] |
| 6 |
| 7 |
| 8 |
| 10 |
| 10 | ns |
| CE |
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tPU |
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| LOW to | 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| ns |
| CE |
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tPD |
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| HIGH to |
| 12 |
| 15 |
| 20 |
| 25 |
| 35 | ns |
| CE |
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WRITE CYCLE[8] |
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tWC |
| Write Cycle Time | 12 |
| 15 |
| 20 |
| 25 |
| 35 |
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tSCE |
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| LOW to Write End | 10 |
| 12 |
| 15 |
| 20 |
| 25 |
| ns |
| CE |
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tAW |
| Address | 10 |
| 12 |
| 15 |
| 20 |
| 25 |
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| End |
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tHA |
| Address Hold from Write | 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| ns | ||
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| End |
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tSA |
| Address | 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| ns | ||
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| Start |
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tPWE |
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| Pulse Width | 10 |
| 12 |
| 15 |
| 20 |
| 25 |
| ns |
| WE |
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tSD |
| Data | 7 |
| 8 |
| 10 |
| 15 |
| 20 |
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tHD |
| Data Hold from Write End | 0 |
| 0 |
| 0 |
| 0 |
| 0 |
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tLZWE |
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| HIGH to Low Z[6] | 3 |
| 3 |
| 3 |
| 3 |
| 3 |
| ns |
| WE |
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tHZWE |
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| LOW to High Z[6, 7] |
| 6 |
| 7 |
| 8 |
| 10 |
| 10 | ns |
| WE |
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Notes:
5.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and
6.At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
7.tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from
8.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data
Document #: | Page 4 of 9 |
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