CY7C107B
CY7C1007B
Features
•High speed
—tAA = 12 ns
•CMOS for optimum speed/power
•Automatic
•
Functional Description
The CY7C107B and CY7C1007B are
1M x 1 Static RAM
Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the ad- dress pins (A0 through A19).
Reading from the devices is accomplished by taking Chip En- able (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location speci- fied by the address pins will appear on the data output (DOUT) pin.
The output pin (DOUT) is placed in a
The CY7C107B is available in a standard
Logic Block Diagram
Pin Configuration
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| INPUT BUFFER |
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A0 |
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| DECODER |
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A1 |
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A2 |
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A3 |
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A4 |
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| 512x2048 |
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A5 |
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| ROW |
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| ARRAY |
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A7 |
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A6 |
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A8 |
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| COLUMN |
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| DECODER |
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| 9 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 |
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| A A A A A A A A A A A |
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| DIN |
AMPS |
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SENSE | DOUT |
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POWER |
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DOWN | CE |
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| WE |
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| SOJ |
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| Top View |
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A10 | 1 | 28 | VCC | |
A11 | 2 | 27 | A | |
A12 | 3 | 26 | 9 | |
A | ||||
A13 |
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4 | 25 | A | ||
A14 |
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5 | A6 | |||
23 | ||||
A15 | 6 | A5 | ||
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NC | 7 | A4 | ||
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A16 | 8 | NC | ||
20 | ||||
A17 | 9 | A3 | ||
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A18 | 10 | 19 | A2 | |
A19 | 11 | 18 | A1 | |
DOUT | 12 | 17 | A0 | |
WE | 13 | 16 | DIN | |
GND | 14 | 15 | CE | |
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Selection Guide
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Maximum Access Time (ns) | 12 | 15 | 20 | 25 | 35 |
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Maximum Operating | 90 | 80 | 75 | 70 | 60 |
Current (mA) |
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Maximum CMOS Standby | 2 | 2 | 2 | 2 | 2 |
Current SB2 (mA) |
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Cypress Semiconductor Corporation • 3901 North First Street | • San Jose • CA 95134 • |
Document #: | Revised September 7, 2001 |
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