Cypress CY7C1007B manual Features, Functional Description, Logic Block Diagram, Pin Configuration

Models: CY7C1007B CY7C107B

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CY7C107B

CY7C107B

CY7C1007B

Features

High speed

tAA = 12 ns

CMOS for optimum speed/power

Automatic power-down when deselected

TTL-compatible inputs and outputs

Functional Description

The CY7C107B and CY7C1007B are high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. These devices have an automatic power-down feature that reduces power consump- tion by more than 65% when deselected.

1M x 1 Static RAM

Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the ad- dress pins (A0 through A19).

Reading from the devices is accomplished by taking Chip En- able (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location speci- fied by the address pins will appear on the data output (DOUT) pin.

The output pin (DOUT) is placed in a high-impedance state when the device is deselected (CE HIGH) or during a write operation (CE and WE LOW).

The CY7C107B is available in a standard 400-mil-wide SOJ; the CY7C1007B is available in a standard 300-mil-wide SOJ.

Logic Block Diagram

Pin Configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPUT BUFFER

 

 

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DECODER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A4

 

 

 

 

 

 

 

512x2048

 

 

 

 

A5

 

 

 

 

 

 

 

 

 

 

 

 

ROW

 

 

 

 

 

 

ARRAY

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COLUMN

 

 

 

 

 

 

 

 

 

 

 

 

DECODER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9 10

11

12

13

14

15

16

17

18

19

 

 

 

 

A A A A A A A A A A A

 

 

 

DIN

AMPS

 

SENSE

DOUT

 

POWER

 

DOWN

CE

 

 

WE

 

107B-1

 

 

SOJ

 

 

Top View

 

A10

1

28

VCC

A11

2

27

A

A12

3

26

9

A

A13

 

 

8

4

25

A

A14

 

24

7

5

A6

23

A15

6

A5

22

NC

7

A4

21

A16

8

NC

20

A17

9

A3

 

A18

10

19

A2

A19

11

18

A1

DOUT

12

17

A0

WE

13

16

DIN

GND

14

15

CE

 

 

 

107B-2

Selection Guide

 

7C107B-12

7C107B-15

7C107B-20

7C107B-25

7C107B-35

 

7C1007B-12

7C1007B-15

7C1007B-20

7C1007B-25

7C1007B-35

 

 

 

 

 

 

Maximum Access Time (ns)

12

15

20

25

35

 

 

 

 

 

 

Maximum Operating

90

80

75

70

60

Current (mA)

 

 

 

 

 

 

 

 

 

 

 

Maximum CMOS Standby

2

2

2

2

2

Current SB2 (mA)

 

 

 

 

 

 

 

 

 

 

 

Cypress Semiconductor Corporation • 3901 North First Street

• San Jose • CA 95134 • 408-943-2600

Document #: 38-05030 Rev. **

Revised September 7, 2001

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Cypress CY7C1007B manual Features, Functional Description, Logic Block Diagram, Pin Configuration, Selection Guide