Features
•High speed
— tAA = 15 ns
•CMOS for optimum speed/power
•Automatic
•
CY7C107BN
CY7C1007BN
1M x 1 Static RAM
Functional Description
The CY7C107BN and CY7C1007BN are
Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A19).
Reading from the devices is accomplished by taking Chip Enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the data output (DOUT) pin.
The output pin (DOUT) is placed in a
The CY7C107BN is available in a standard
Logic Block Diagram |
|
|
| |||||||
|
|
|
|
|
|
|
|
|
| DIN |
A0 |
|
| INPUT BUFFER |
|
| |||||
DECODERROW |
|
|
|
|
|
|
| AMPSSENSE |
| |
A7 |
|
|
|
|
|
|
|
| ||
A1 |
|
|
|
|
|
|
|
|
|
|
A2 |
|
|
|
|
|
|
|
|
|
|
A3 |
|
|
|
|
|
|
|
|
|
|
A4 |
|
| 512 x 2048 |
|
|
| ||||
A5 |
|
|
| ARRAY |
|
| DOUT | |||
A6 |
|
|
|
|
|
|
|
|
| |
A8 |
|
|
|
|
|
|
|
|
|
|
|
|
| COLUMN |
|
| POWER |
| |||
|
|
|
|
| DOWN | CE | ||||
|
|
| DECODER |
|
|
| ||||
|
|
|
|
|
|
| ||||
| 9 | 10 11 | 12 13 | 14 | 15 | 16 | 17 18 | 19 |
| WE |
| A |
| ||||||||
| A A A A A A A A A A |
|
|
Pin Configuration
|
| SOJ |
| |
| Top View |
| ||
A10 | 1 | 28 | VCC | |
A11 | 2 | 27 | A | |
A12 | 3 | 26 | A9 | |
A13 | 4 | 25 | A8 | |
A14 |
| 24 | 7 | |
5 | A6 | |||
23 | ||||
A15 | 6 | A5 | ||
22 | ||||
NC | 7 | A4 | ||
21 | ||||
A16 | 8 | NC | ||
20 | ||||
A17 | 9 | A3 | ||
19 | ||||
A | 10 | A | ||
A18 | 11 | 18 | A2 | |
DOUT19 | 12 | 17 | A01 | |
WE | 13 | 16 | DIN | |
GND | 14 | 15 | CE |
Selection Guide
|
|
|
| |
|
|
|
| |
Maximum Access Time (ns) |
| 15 |
|
|
Maximum Operating Current (mA) |
| 80 |
|
|
Maximum CMOS Standby Current ISB2 (mA) |
| 2 |
|
|
Cypress Semiconductor Corporation • | 198 Champion Court • San Jose, CA | • | ||
Document #: |
| Revised February 1, 2006 |
[+] Feedback