Cypress manual CY7C107BN CY7C1007BN, Features, Functional Description, Logic Block Diagram

Models: CY7C107BN CY7C1007BN

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Features

Features

High speed

— tAA = 15 ns

CMOS for optimum speed/power

Automatic power-down when deselected

TTL-compatible inputs and outputs

CY7C107BN

CY7C1007BN

1M x 1 Static RAM

Functional Description

The CY7C107BN and CY7C1007BN are high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected.

Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A19).

Reading from the devices is accomplished by taking Chip Enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the data output (DOUT) pin.

The output pin (DOUT) is placed in a high-impedance state when the device is deselected (CE HIGH) or during a write operation (CE and WE LOW).

The CY7C107BN is available in a standard 400-mil-wide SOJ; the CY7C1007BN is available in a standard 300-mil-wide SOJ

Logic Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

DIN

A0

 

 

INPUT BUFFER

 

 

DECODERROW

 

 

 

 

 

 

 

AMPSSENSE

 

A7

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

 

A2

 

 

 

 

 

 

 

 

 

 

A3

 

 

 

 

 

 

 

 

 

 

A4

 

 

512 x 2048

 

 

 

A5

 

 

 

ARRAY

 

 

DOUT

A6

 

 

 

 

 

 

 

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

 

 

COLUMN

 

 

POWER

 

 

 

 

 

 

DOWN

CE

 

 

 

DECODER

 

 

 

 

 

 

 

 

 

 

 

9

10 11

12 13

14

15

16

17 18

19

 

WE

 

A

 

 

A A A A A A A A A A

 

 

Pin Configuration

 

 

SOJ

 

 

Top View

 

A10

1

28

VCC

A11

2

27

A

A12

3

26

A9

A13

4

25

A8

A14

 

24

7

5

A6

23

A15

6

A5

22

NC

7

A4

21

A16

8

NC

20

A17

9

A3

19

A

10

A

A18

11

18

A2

DOUT19

12

17

A01

WE

13

16

DIN

GND

14

15

CE

Selection Guide

 

 

7C107BN-15

 

 

 

 

7C1007BN-15

 

 

Maximum Access Time (ns)

 

15

 

 

Maximum Operating Current (mA)

 

80

 

 

Maximum CMOS Standby Current ISB2 (mA)

 

2

 

 

Cypress Semiconductor Corporation

198 Champion Court • San Jose, CA 95134-1709

408-943-2600

Document #: 001-06426 Rev. **

 

Revised February 1, 2006

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Cypress manual CY7C107BN CY7C1007BN, Features, Functional Description, Logic Block Diagram, Pin Configuration