CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *F Page 15 of 28
Identification Register Definitions
Instruction Field CY7C1372D CY7C1370D Description
Revision Number (31:29) 000 000 Reserved for version number.
Cypress Device ID (28:12)[12] 01011001000100101 01011001000010101 Reserved for future use.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence (0) 1 1 Indicate the presence of an ID register.
Scan Register Sizes
Register Name Bit Size (x18) Bit Size (x36)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan Order (119-ball BGA package) 85 85
Boundary Scan Order (165-ball FBGA package) 89 89
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM opera-
tions.
Note:
12.Bit #24 is “1” in the Register Definitions for both 2.5Vand 3.3V versions of this device.
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