Cypress CY7C1370D, CY7C1372D Ordering Information

CY7C1370D

CY7C1372D

Document #: 38-05555 Rev. *F Page 24 of 28

250 CY7C1370D-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1372D-250AXC

CY7C1370D-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372D-250BGC

CY7C1370D-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1372D-250BGXC

CY7C1370D-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1372D-250BZC

CY7C1370D-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1372D-250BZXC

CY7C1370D-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

CY7C1372D-250AXI

CY7C1370D-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1372D-250BGI

CY7C1370D-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1372D-250BGXI

CY7C1370D-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1372D-250BZI

CY7C1370D-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1372D-250BZXI

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

[+] Feedback

Contents

Main 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL Architecture CY7C1370D CY7C1372D Features Functional Description Logic Block Diagram-CY7C1370D (512K x 36) CY7C1370D CY7C1372D Document #: 38-05555 Rev. *F Page 2 of 28 Selection Guide A0, A1, A C ZZ CY7C1370D CY7C1372D Document #: 38-05555 Rev. *F Page 3 of 28 Pin Configurations (512K 36) (1M 18) MODE Pin Configurations 2345671 A B C D E F G H J K L M N P R T U CY7C1370D (512K x 36) 119-Ball BGA Pinout 2345671 A B C D E F G H J K L M N P R T U Pin Configurations CY7C1370D (512K x 36) 2345671 A B C D E F G H J K L M N P R CY7C1372D (1M x 18) 891011 Pin Definitions CY7C1370D CY7C1372D Introduction Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Partial Write Cycle Description IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Page CY7C1370D CY7C1372D TAP Timing TAP AC Switching Characteristics 3.3V TAP AC Test Conditions 3.3V TAP AC Output Load Equivalent F DO T Identification Register Definitions Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order 165-Ball BGA Boundary Scan Order Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read/Write/Timing OE n-Out (DQ) I Switching Waveforms CLK ZZ LL INPUTS (except ZZ) DONT CARE Page Ordering Information Package Diagrams A 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) Package Diagrams 0.900.05 51-85115-*B 0.56 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Package Diagrams 51-85180-*A SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A Document History Page