Cypress CY7C150 manual

CY7C150

Features

•Memory reset function

•1024 x 4 static RAM for control store in high-speed com- puters

•CMOS for optimum speed/power

•High speed

—10 ns (commercial)

—12 ns (military)

•Low power

—495 mW (commercial)

—550 mW (military)

•Separate inputs and outputs

•5-volt power supply ± 10% tolerance in both commercial and military

•Capable of withstanding greater than 2001V static dis- charge

•TTL-compatible inputs and outputs

1Kx4 Static RAM

Separate I/O paths eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable (OE) is held HIGH, allowing for easy memory expansion.

Reset is initiated by selecting the device (CS = LOW) and taking the reset (RS) input LOW. Within two memory cycles all bits are internally cleared to zero. Since chip select must be LOW for the device to be reset, a global reset signal can be employed, with only selected devices being cleared at any given time.

Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the four data inputs (D0− D3) is written into the memory location specified on the address pins (A0 through A9).

Reading the device is accomplished by taking chip select (CS) and output enable (OE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O0 through O3).

Functional Description

The CY7C150 is a high-performance CMOS static RAM designed for use in cache memory, high-speed graphics, and data-acquisition applications. The CY7C150 has a memory reset feature that allows the entire memory to be reset in two memory cycles.

The output pins remain in high-impedance state when chip enable (CE) or output enable (OE) is HIGH, or write enable (WE) or reset (RS) is LOW.

A die coat is used to insure alpha immunity.

Logic Block Diagram

			D0 D1 D2 D3
			DATAINPUT
			CONTROL
A0	DECODER
A1				64 x 64
A2
A3	ROW			ARRAY
A4
A5
				COLUMN
			DECODER
		A6		A7 A8 A9

SENSE AMPS

Pin Configuration

RS

				DIP/SOIC
		CS
				Top View
		OE	A3					VCC
				1		24
		WE
			A4	2	23			A2
			A5	3	22			A1
	O0		A6	4	21			A0
			A7	5	20
								RS
			A8	6 7C150 19
		O1						CS
			A9
				7	18			WE
			D0	8	17
		O2							OE
			D1	9	16			D3
				10
			O0		15				D
	O3		O1	11	14		2
									O
							3
			GND	12	13				O2
C150–1							C150-2

Selection Guide

			7C150− 10	7C150− 12	7C150− 15		7C150− 25	7C150− 35
	Maximum Access Time (ns)	Commercial	10	12	15		25
		Military		12	15		25	35
	Maximum Operating Current (mA)	Commercial	90	90	90		90	90
		Military		100	100		100	100
Cypress Semiconductor Corporation		• 3901 North First Street		• San Jose	• CA	95134 • 408-943-2600
Document #: 38-05024 Rev. **							Revised August 24, 2001