Cypress CY7C150 Switching Waveforms (continued)

CY7C150

Switching Waveforms (continued)

Write Cycle No2. (CS Controlled) [8,12]

tWC

ADDRESS

tSA

tSCS

CE

tAW

tHA

tPWE

WE

tSD

tHD

DATA IN

DATA IN VALID

tHZWE

HIGH IMPEDANCE

DATA I/O

DATA UNDEFINED

C150-8

Reset Cycle [13]

ADDRESS

tRRC

tSAR

t

HAR

WE

tSWER

tHCSR

tHWER

tSCSR

CS

tPRS

RESET

tHZRS

DATA I/O

tLZRS

HIGH

IMPEDANCE

OUTPUT VALID ZERO

C150-9

Notes:

12.If CS goes HIGH with WE HIGH, the output remains in a high-impedance state.

13.Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.

Document #: 38-05024 Rev. **

Page 5 of 11

Contents

Features Functional Description Logic Block Diagram Pin Configuration Selection Guide Maximum Ratings Electrical Characteristics Over the Operating Range[2] Operating Range Capacitance[4] AC Test Loads and Waveforms Switching Characteristics Over the Operating Range[2,5] Switching Waveforms Switching Waveforms (continued) Typical DC and AC Characteristics Truth Table Ordering Information MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Package Diagrams Package Diagrams (continued)