CY7C1516AV18, CY7C1527AV18
CY7C1518AV18, CY7C1520AV18
Switching Characteristics
Over the Operating Range [20, 21]
| Cypress | Consortium |
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| Description | 300 MHz | 278 MHz | 250 MHz | 200 MHz | 167 MHz | Unit | ||||||||||||||||||||
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| Min | Max | Min | Max | Min | Max | Min | Max | Min | Max | ||||||||||||||||||
t | POWER |
| V (Typical) to the First Access [22] | 1 | – | 1 | – | 1 | – | 1 | – | 1 | – | ms | |||||||||||||||||||
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tCYC | tKHKH | K Clock and C Clock Cycle Time | 3.3 | 8.4 | 3.6 | 8.4 | 4.0 | 8.4 | 5.0 | 8.4 | 6.0 | 8.4 | ns | ||||||||||||||||||||
tKH | tKHKL |
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Input Clock (K/K | and C/C) HIGH | 1.32 | – | 1.4 | – | 1.6 | – | 2.0 | – | 2.4 | – | ns | |||||||||||||||||||||
tKL | tKLKH |
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Input Clock (K/K | and C/C) LOW | 1.32 | – | 1.4 | – | 1.6 | – | 2.0 | – | 2.4 | – | ns | |||||||||||||||||||||
tKHKH | tKHKH | K Clock Rise to |
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| Clock Rise and C | 1.49 | – | 1.6 | – | 1.8 | – | 2.2 | – | 2.7 | – | ns | |||||||||||||||||
K | |||||||||||||||||||||||||||||||||
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| to C Rise (rising edge to rising edge) |
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tKHCH | tKHCH |
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K/K | Clock Rise to C/C Clock Rise | 0.0 | 1.45 | 0.0 | 1.55 | 0.0 | 1.8 | 0.0 | 2.2 | 0.0 | 2.7 | ns | |||||||||||||||||||||
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Setup Times |
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tSA | tAVKH | Address Setup to K Clock Rise | 0.4 | – | 0.4 | – | 0.5 | – | 0.6 | – | 0.7 | – | ns | ||||||||||||||||||||
tSC | tIVKH | Control Setup to K Clock Rise | 0.4 | – | 0.4 | – | 0.5 | – | 0.6 | – | 0.7 | – | ns | ||||||||||||||||||||
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tSCDDR | tIVKH | Double Data Rate Control Setup to | 0.3 | – | 0.3 | – | 0.35 | – | 0.4 | – | 0.5 | – | ns | ||||||||||||||||||||
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| (BWS0, BWS1, | BWS | 2, | BWS | 3) |
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tSD [23] | tDVKH |
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| Rise | 0.3 | – | 0.3 | – | 0.35 | – | 0.4 | – | 0.5 | – | ns | ||
D[X:0] Setup to Clock (K/K) | |||||||||||||||||||||||||||||||||
Hold Times |
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tHA | tKHAX | Address Hold after K Clock Rise | 0.4 | – | 0.4 | – | 0.5 | – | 0.6 | – | 0.7 | – | ns | ||||||||||||||||||||
tHC | tKHIX | Control | Hold after K Clock Rise | 0.4 | – | 0.4 | – | 0.5 | – | 0.6 | – | 0.7 | – | ns | |||||||||||||||||||
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tHCDDR | tKHIX | Double Data Rate Control Hold after | 0.3 | – | 0.3 | – | 0.35 | – | 0.4 | – | 0.5 | – | ns | ||||||||||||||||||||
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| (BWS0, BWS1, | BWS | 2, | BWS | 3) |
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tHD | tKHDX |
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| Rise | 0.3 | – | 0.3 | – | 0.35 | – | 0.4 | – | 0.5 | – | ns | ||
D[X:0] Hold after Clock (K/K) | |||||||||||||||||||||||||||||||||
Notes
21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.
22.This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated.
23.For DQ0 data signal on CY7C1527AV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
Document Number: | Page 23 of 30 |
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