Ordering Information | Cypress CY7C1516AV18, CY7C1527AV18 instruction

CY7C1516AV18, CY7C1527AV18

CY7C1518AV18, CY7C1520AV18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1516AV18-300BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1527AV18-300BZC

	CY7C1518AV18-300BZC

	CY7C1520AV18-300BZC

	CY7C1516AV18-300BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527AV18-300BZXC

	CY7C1518AV18-300BZXC

	CY7C1520AV18-300BZXC

	CY7C1516AV18-300BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1527AV18-300BZI

	CY7C1518AV18-300BZI

	CY7C1520AV18-300BZI

	CY7C1516AV18-300BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527AV18-300BZXI

	CY7C1518AV18-300BZXI

	CY7C1520AV18-300BZXI

278	CY7C1516AV18-278BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1527AV18-278BZC

	CY7C1518AV18-278BZC

	CY7C1520AV18-278BZC

	CY7C1516AV18-278BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527AV18-278BZXC

	CY7C1518AV18-278BZXC

	CY7C1520AV18-278BZXC

	CY7C1516AV18-278BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1527AV18-278BZI

	CY7C1518AV18-278BZI

	CY7C1520AV18-278BZI

	CY7C1516AV18-278BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527AV18-278BZXI

	CY7C1518AV18-278BZXI

	CY7C1520AV18-278BZXI

Document Number: 001-06982 Rev. *D

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Cypress CY7C1516AV18, CY7C1527AV18, CY7C1520AV18, CY7C1518AV18 manual Ordering Information

Contents

Functional Description FeaturesConfigurations Selection Guide Doff Logic Block Diagram CY7C1516AV18Logic Block Diagram CY7C1527AV18 CLK BWS Logic Block Diagram CY7C1518AV18Logic Block Diagram CY7C1520AV18 CY7C1516AV18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1527AV18 8M x CY7C1518AV18 4M x CY7C1520AV18 2M x Synchronous Read or Write input. When Pin DefinitionsPin Name Pin Description TDO for Jtag Power supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for Jtag DDR Operation Single Clock ModeFunctional Overview Programmable Impedance Application ExampleDepth Expansion Echo Clocks First Address External Second Address Internal Write Cycle DescriptionsOperation BWS0/ BWS1 NWS0 NWS1 BWS0 BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TDI TAP Controller Block DiagramTAP Electrical Characteristics TCK TAP AC Switching Characteristics TAP Timing and Test Conditions Instruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit Size Boundary Scan Order Bit # Bump ID DLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga Unit Switching Characteristics Static to DLL Reset DLL Timing Read Switching WaveformsNOP NOP Write Read Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mm REV ECN no Submission ORIG. Description of Change Date Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions