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Cypress CY7C1516AV18, CY7C1518AV18, CY7C1520AV18, CY7C1527AV18 Ordering Information

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CY7C1516AV18, CY7C1527AV18

CY7C1518AV18, CY7C1520AV18

Document Number: 001-06982 Rev. *D Page 28 of 30

167 CY7C1516AV18-167BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1527AV18-167BZC

CY7C1518AV18-167BZC

CY7C1520AV18-167BZC

CY7C1516AV18-167BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1527AV18-167BZXC

CY7C1518AV18-167BZXC

CY7C1520AV18-167BZXC

CY7C1516AV18-167BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1527AV18-167BZI

CY7C1518AV18-167BZI

CY7C1520AV18-167BZI

CY7C1516AV18-167BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1527AV18-167BZXI

CY7C1518AV18-167BZXI

CY7C1520AV18-167BZXI

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

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Contents

Main 72-Mbit DDR-II SRAM 2-Word Burst Architecture CY7C1516AV18, CY7C1527AV18 CY7C1518AV18, CY7C1520AV18 Features Configurations Functional Description CY7C1516AV18, CY7C1527AV18 CY7C1518AV18, CY7C1520AV18 Document Number: 001-06982 Rev. *D Page 2 of 30 Logic Block Diagram (CY7C1516AV18) Logic Block Diagram (CY7C1527AV18) 4M x 8 Array 4M x 8 Array Logic Block Diagram (CY7C1518AV18) Logic Block Diagram (CY7C1520AV18) 2M x 18 Array 2M x 18 Array 1M x 36 Array 1M x 36 Array Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1516AV18, CY7C1527AV18 CY7C1518AV18, CY7C1520AV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1516AV18, CY7C1527AV18 Pin Definitions CY7C1516AV18, CY7C1527AV18 CY7C1518AV18, CY7C1520AV18 Pin Definitions CY7C1516AV18, CY7C1527AV18 CY7C1518AV18, CY7C1520AV18 Functional Overview Single Clock Mode DDR Operation Application Example SRAM#1 SRAM#2 BUS MASTER (CPU or ASIC) Truth Table Burst Address Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Page TAP Controller State Diagram CY7C1516AV18, CY7C1527AV18 CY7C1518AV18, CY7C1520AV18 TAP Controller Block Diagram TAP Electrical Characteristics CY7C1516AV18, CY7C1527AV18 TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1516AV18, CY7C1527AV18 CY7C1518AV18, CY7C1520AV18 Boundary Scan Order Power Up Sequence in DDR-II SRAM VV Power Up Sequence DLL Constraints / CY7C1518AV18, CY7C1520AV18 Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Page Switching Characteristics Document Number: 001-06982 Rev. *D Page 25 of 30 Switching Waveforms Figure 5. Read/Write/Deselect Sequence READ READREAD NOP NOP WRITEWRITE NOP 12345678910 Ordering Information CY7C1516AV18, CY7C1527AV18 Ordering Information Document Number: 001-06982 Rev. *D Page 29 of 30 Package Diagram [+] Feedback Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85195 51-85195-*A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page