167 | Cypress CY7C1527AV18, CY7C1520AV18, CY7C1516AV18, CY7C1518AV18

CY7C1516AV18, CY7C1527AV18

CY7C1518AV18, CY7C1520AV18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
167	CY7C1516AV18-167BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1527AV18-167BZC

	CY7C1518AV18-167BZC

	CY7C1520AV18-167BZC

	CY7C1516AV18-167BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527AV18-167BZXC

	CY7C1518AV18-167BZXC

	CY7C1520AV18-167BZXC

	CY7C1516AV18-167BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1527AV18-167BZI

	CY7C1518AV18-167BZI

	CY7C1520AV18-167BZI

	CY7C1516AV18-167BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1527AV18-167BZXI

	CY7C1518AV18-167BZXI

	CY7C1520AV18-167BZXI

Document Number: 001-06982 Rev. *D

Page 28 of 30

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Cypress CY7C1527AV18, CY7C1520AV18, CY7C1516AV18, CY7C1518AV18 manual 167

Contents

Features ConfigurationsFunctional Description Selection Guide Logic Block Diagram CY7C1516AV18 Logic Block Diagram CY7C1527AV18Doff CLK Logic Block Diagram CY7C1520AV18 Logic Block Diagram CY7C1518AV18BWS Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1516AV18 8M x CY7C1527AV18 8M x CY7C1518AV18 4M x CY7C1520AV18 2M x Pin Name Pin Description Pin DefinitionsSynchronous Read or Write input. When Power supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for Jtag Functional Overview Single Clock ModeDDR Operation Application Example Depth ExpansionProgrammable Impedance Echo Clocks Write Cycle Descriptions OperationFirst Address External Second Address Internal BWS0/ BWS1 NWS0 NWS1 BWS0 BWS0 BWS1 BWS2 BWS3 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCK TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register SizesInstruction Codes Register Name Bit Size Boundary Scan Order Bit # Bump ID Power Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga Unit Switching Characteristics Static to DLL Reset DLL Timing Switching Waveforms NOPRead NOP Write Read Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mm Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationREV ECN no Submission ORIG. Description of Change Date