Cypress STK22C48 Switching Waveforms

STK22C48
Document Number: 001-51000 Rev. ** Page 9 of 14
SRAM Write Cycle
Parameter Description 25 ns 45 ns Unit
Min Max Min Max
Cypress
Parameter Alt
tWC tAVAV Write Cycle Time 25 45 ns
tPWE tWLWH, tWLEH Write Pulse Width 20 30 ns
tSCE tELWH, tELEH Chip Enable To End of Write 20 30 ns
tSD tDVWH, tDVEH Data Setup to End of Write 10 15 ns
tHD tWHDX, tEHDX Data Hold After End of Write 0 0 ns
tAW tAVWH, tAVEH Address Setup to End of Write 20 30 ns
tSA tAVWL, tAVEL Address Setup to Start of Write 0 0 ns
tHA tWHAX, tEHAX Address Hold After End of Write 0 0 ns
tHZWE [8,9] tWLQZ Write Enable to Output Disable 10 14 ns
tLZWE [8] tWHQX Output Active After End of Write 5 5 ns
Switching Waveforms Figure 9. SRAM Write Cycle 1: WE Controlled [10, 11]
Figure 10. SRAM Write Cycle 2: CE Controlled [10, 11]
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT HIGH IMPEDANCE
DATA VALID
Notes
9. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
10.HSB must be high during SRAM Write cycles.
11. CE or WE must be greater than VIH during address transitions.
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